在新一代無線通訊系統, 多重輸入輸出(Multiple-Input Multiple-Output, MIMO) 正交分頻多工(Orthogonal Frequency Division Multiplexing) 的技術中, 快速傅立葉轉換(Fast Fourier Transform, FFT) 佔有相當大的重要性。而快速傅立葉轉換處理器最基本的元件,蝴蝶運算器(butterfly) 會因等待資料的輸入而導致整體硬體使用率的下降。我們利用適當大小的前授記憶體(feed forward memory) 提昇蝴蝶運算器的硬體使用率, 且將之用於多重
輸入輸出系統上。且利用適當的記憶體配置方式, 妥善利用回授記憶體, 來降低其硬體複雜度。我們提供傅立葉點數128到2048可變長度的快速傅立葉處理器, 而針對多種傅立葉長度的設計, 在演算法上, 我們使用二維拆解(two-dimensional decompose) 及基底42的方式。
基底42高基底演算法, 可以減少複數乘法的產生, 而使用二維拆解的方式, 分別處理四冪次方及非四冪次方的傅立葉點數。最後, 我們將此用於4X4多重輸入輸出系統的可變長度快速傅立葉轉換器實現成硬體。最後我們以Cell-based 的設計方式, 將此架構實現於晶片。使用製程為UMC 90um , 核心面積(core area) 為2.14987mm2 , 操作頻率在83.3MHz , 符合3GPP-LTE 的規範。

In this paper, we present a variable-length 256-point to 2048-point FFT processor for
4x4 Multiple Input Multiple Output(MIMO) Orthogonal Frequency Division Multiplex-
ing(OFDM) systems. In general, the amount the FFT processors for MIMO system are
dependent on the maximum required of data sequences and the basic unit butterfly has
the 1/r idle time where r is radix-r. It is area-ineffective for VLSI implement. By the
proposed butterfly sharing technique, the effective hardware utilization can be improved
to 100%. The radix-42 algorithm is sufficient to deal with the four data sequences simul-
taneous and reduce the hardware complexity and cost. The signal quantization noise
ratio(SQNR) is over 43 dB for QPSK and 16/64-QAM signals. Moreover we imple-
ment the variable length FFT processor in UMC 90um technology. The core area is
3.193248mm2 with 83.3MHz.

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