本篇論文針對低密度奇偶檢查碼 (Low-density parity-check codes, LDPC codes)階層式架構(Layered scheduling)解碼器分別提出幾種改良演算法、硬體架構以及電路設計的方法來提升的解碼吞吐量以及降低硬體複雜度。由於LDPC 解碼演算法之解碼複雜度與大量儲存資訊的要求主要都是來自檢查節點更新的計算，因此本文第一個方法提出了只存第二小值(second-minimum-only, SMO)的正規化最小和演算法(normalized Min-Sum, NMS)來降低檢查節點更新的儲存量且不會有太大的解碼效能衰退。

為了能夠達到更高解碼吞吐量的解碼器且不影響解碼效能，一種時間維度(Time-domain, TD)的訊號處理方式與電路設計敘述在本篇論文的第四章中。透過TD訊號處理技巧使得LDPC解碼器在檢查節點(check node, CN)運算的時間可以大幅下降。一個Q-based的階層解碼器架構被用來減少C2V資訊儲存量。本篇論文利用IEEE 802.15.3c標準做為展示TD-based 的技術，此顆晶片採用CMOS 90奈米製程，核心電路面積為2.25 mm$^2$。量測結果在1.05V的操作電壓下，操作頻率最高可以達157 MHz，此時的解碼吞吐量為5.28 Gbps，能量消耗與能源效率分別為182 mW、34.47 pJ/b。這是第一顆利用TD訊號處理方式可以實作在通訊標準的晶片設計。

相較於二進制(binary)運算，利用高維度的有限域(high-order finite field)運算的非二進制(non-binary, NB)LDPC碼可以擁有更好的解碼效能，然而其運算複雜度與儲存資訊需求亦提高不少。本篇論文第五章節針對Trellis Min-Max (TMM)演算法提出一個適合硬體設計的低複雜度演算法以及高硬體效率的解碼器架構來達到傳統NB-LDPC解碼器難以做到的高吞吐量與低硬體面積的需求。為了減少CN資訊的儲存量以及避免解碼效能衰退，論文提出了適合硬體設計的CN資訊的壓縮與解壓縮的技術，此方法亦可減低運算需求。此外，一個有效率的後驗概率({\it a posteriori} log-likelihood ratio)計算方式也被提出來達到減低運算複雜度。為了做到更高的解碼吞吐量，我們提出第一個實作在NB-LDPC解碼器且不會影響解碼效能的提早終止方式。利用與CN運算共用計算模組，此提早終止方式不需要花費太多額外的硬體代價以及不需增加額外運算時間。以上技術利用90奈米製程展示在32-ary (837, 726)的NB-LDPC碼，其解碼器硬體面積為6.86 mm$^2$，模擬的操作頻率最高可達526.32 MHz，在提早終止尚未啟動時，解碼吞吐量為1.64 Gbps，如果在$E_b/N_0 = $ 4.5 dB情況下啟動提早終止功能時，解碼吞吐量可以再提升至4.68 Gbps。與過去文獻比較，即使不使用提早終止功能，本解碼器仍可達到最高解碼吞吐量以及最高的硬體效能。

In order to further enhance the hardware efficiency for a low-density parity-check (LDPC) decoder, the decoding algorithm, together with the associated architecture should be modified.
No matter whether the LDPC deocder is binary or non-binary(NB), the process for updating the check-node (CN) unit dominates the decoding complexity and memory requirements.
For a binary LDPC decoder, a second minimum-only Normalized Min-Sum (NMS) algorithm is proposed such that the first minimum values are not stored without introducing any notable degradation in error-rate performance.
Therefore, only second minimum values, together with the associated index of the first minimum value need to be stored.

In order to achieve a further high-throughput LDPC decoder while preventing any degradation in error-rate performance, a time-domain (TD) signal processing scheme is proposed.
The latency for determining the first two minimum values required in the CN unit is significantly reduced through TD processing.
A layered Q-based decoding architecture, together with the associated scheduling, is proposed in order to reduce the amount of memory used for check-to-variable (C2V) storage.
As a proof of concept, a TD-based multi-mode LDPC decoder applicalbe for high-speed IEEE 802.15.3c-compliant devices is designed and fabricated in a 90-nm CMOS process.
The LDPC decoder integrates 495K logic gates in an area of 2.25 mm$^2$, and achieves a throughput of 5.28 Gbps at 157 MHz from a 1.05 V supply voltage.
The power and normalized energy dissipation are 182 mW and 34.47 pJ/b, respectively.
The proposed LDPC decoder is more hardware and energy efficient than its previous digital counterparts, and is able to support long codes for practical applications, which is still unfeasible for the current state-of-the-art TD-based LDPC decoders.

A modified Trellis Min-Max (T-MM) algorithm, together with the associated architecture for NB-LDPC codes, is able to provide a reduction in the memory requirements for CN messages through an efficient indirect method, while enhancing the error-rate performance using appropriate decompression.
A method of updating the {\it a posteriori} log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity.
In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions from the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error-rate performance.
As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process.
The proposed decoder achieves a throughput of 1.64 Gbps at 526.32 MHz with 8 iterations, and has an area of 6.86 mm$^2$.
When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gbps.
The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the current state-of-the-art decoders even when the ET scheme is not enabled.

[1] R. Gallager, “Low-density parity-check codes,” IRE Transactions on In- formation Theory, vol. 8, no. 1, pp. 21–28, Jan. 1962.
[2] D. J. C. MacKay, “Good error-correcting codes based on very sparse ma- trices,” IEEE Transactions on Information Theory, vol. 45, no. 2, pp. 399–431, Mar. 1999.
[3] J. Chen and M. P. C. Fossorier, “Density evolution for two improved BP-based decoding algorithms of LDPC codes,” IEEE Communications Letters, vol. 6, no. 5, pp. 208–210, May 2002.
[4] E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, “High throughput low- density parity-check decoder architectures,” Global Telecommunications Conference, 2001. GLOBECOM ’01. IEEE, vol. 5, 2001, pp. 3019–3024 vol.5.
[5] S. W. Yen, S. Y. Hung, C. L. Chen, H. C. Chang, S. J. Jou, and C. Y. Lee, “A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE

802.15.3c applications,” IEEE Journal of Solid-State Circuits, vol. 47, no. 9, pp. 2246–2257, Sep. 2012.
[6] Z. Chen, X. Peng, X. Zhao, Q. Xie, L. Okamura, D. Zhou, and S. Goto, “A 6.72-Gb/s 8pj/bit/iteration IEEE 802.15.3c LDPC decoder chip,” 2011 International Symposium on Integrated Circuits, Dec 2011, pp. 7–12.
[7] Y. S. Park, D. Blaauw, D. Sylvester, and Z. Zhang, “Low-power high- throughput LDPC decoder using non-refresh embedded DRAM,” IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 783–794, Mar. 2014.
[8] A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate- 1/2 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404–412, Mar. 2002.
[9] S. Kumawat, R. Shrestha, N. Daga, and R. Paily, “High-throughput LDPC-decoder architecture using efficient comparison techniques & dy- namic multi-frame processing schedule,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 5, pp. 1421–1430, May 2015.
[10] Y. Lee, B. Kim, J. Jung, and I. C. Park, “Low-complexity tree architecture for finding the first two minima,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 1, pp. 61–64, Jan. 2015.
[11] D. Wu, Y. Chen, Q. Zhang, Y. l. Ueng, and X. Zeng, “Strategies for re- ducing decoding cycles in stochastic LDPC decoders,” IEEE Transactions

on Circuits and Systems II: Express Briefs, vol. 63, no. 9, pp. 873–877, Sep. 2016.
[12] Y. L. Ueng, C. Y. Wang, and M. R. Li, “An efficient combined bit-flipping and stochastic LDPC decoder using improved probability tracers,” IEEE Transactions on Signal Processing, vol. 65, no. 20, pp. 5368–5380, Oct. 2017.
[13] A. Darabiha, A. C. Carusone, and F. R. Kschischang, “A bit-serial ap- proximate Min-Sum LDPC decoder and FPGA implementation,” in 2006 IEEE International Symposium on Circuits and Systems, May 2006, pp. 4.
[14] C. C. Cheng, J. D. Yang, H. C. Lee, C. H. Yang, and Y. L. Ueng, “A fully parallel LDPC decoder architecture using probabilistic Min-Sum algo- rithm for high-throughput applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 9, pp. 2738–2746, Sep. 2014.
[15] M. R. Li, H. C. Chou, Y. L. Ueng, and Y. Chen, “A low-complexity LDPC decoder for NAND flash applications,” IEEE International Symposium on Circuits and Systems (ISCAS), Jun. 2014, pp. 213–216.
[16] J. Kim, J. Cho, and W. Sung, “A high-speed layered Min-Sum LDPC decoder for error correction of NAND flash memories,” IEEE 54th Inter-

national Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2011, pp. 1–4.
[17] J. Kim and W. Sung, “Rate-0.96 LDPC decoding VLSI for soft-decision error correction of NAND flash memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1004–1015, May 2014.
[18] H. C. Lee, M. R. Li, J. K. Hu, P. C. Chou, and Y. L. Ueng, “Optimization techniques for the efficient implementation of high-rate layered QC-LDPC decoders,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 457–470, Feb. 2017.
[19] C. L. Wey, M. D. Shieh, and S. Y. Lin, “Algorithms of finding the first two minimum values and their hardware implementation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3430–3437, Dec. 2008.
[20] D. Miyashita, R. Yamaki, K. Hashiyoshi, H. Kobayashi, S. Kousai,

Y. Oowaki, and Y. Unekawa, “An LDPC decoder with time-domain ana- log and digital mixed-signal processing,” IEEE Journal of Solid-State Cir- cuits, vol. 49, no. 1, pp. 73–83, Jan. 2014.
[21] M. C. Davey and D. MacKay, “Low-density parity check codes over GF(q),” IEEE Communications Letters, vol. 2, no. 6, pp. 165–167, Jun.

1998.

[22] C. Spagnol and W. Marnane, “A class of quasi-cyclic LDPC codes over GF(2m),” IEEE Transactions on Communications, 2009.
[23] W. Chang and J. R. Cruz, “Performance and decoding complexity of nonbinary LDPC codes for magnetic recording,” IEEE Transactions on Magnetics, vol. 44, no. 1, pp. 211–216, Jan. 2008.
[24] F. Guo and L. Hanzo, “Low complexity non-binary LDPC and modula- tion schemes communicating over MIMO channels,” IEEE 60th Vehicular Technology Conference, 2004. VTC2004-Fall. 2004, vol. 2, Sep. 2004, pp. 1294–1298 Vol. 2.
[25] S. Pfletschinger and D. Declercq, “Getting closer to MIMO capacity with non-binary codes and spatial multiplexing,” 2010 IEEE Global Telecom- munications Conference GLOBECOM 2010, Dec. 2010, pp. 1–5.
[26] J. Thorpe, “Low-density parity-check (LDPC) codes constructed from protographs,” JPL INP, Tech. Rep., pp. 42–154, Aug. 2003.
[27] S. Hemati, A. H. Banihashemi, and C. Plett, “A 0.18-µm CMOS analog Min-Sum iterative decoder for a (32,8) low-density parity-check (LDPC) code,” IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2531– 2540, Nov. 2006.

[28] M. Gu and S. Chakrabartty, “A 100 pJ/bit, (32,8) CMOS analog low- density parity-check decoder based on margin propagation,” IEEE Jour- nal of Solid-State Circuits, vol. 46, no. 6, pp. 1433–1442, Jun. 2011.
[29] T. Mohsenin, D. N. Truong, and B. M. Baas, “A Low-complexity message- passing algorithm for reduced routing congestion in LDPC decoders,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 5, pp. 1048–1061, May 2010.
[30] A. Darabiha, A. C. Carusone, and F. R. Kschischang, “Power reduction techniques for LDPC decoders,” IEEE Journal of Solid-State Circuits, vol. 43, no. 8, pp. 1835–1845, Aug. 2008.
[31] F. Angarita, J. Valls, V. Almenar, and V. Torres, “Reduced-complexity Min-Sum algorithm for decoding LDPC codes with low error-floor,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 7, pp. 2150–2158, Jul. 2014.
[32] A. Balatsoukas-Stimming, N. Preyss, A. Cevrero, A. Burg, and C. Roth, “A parallelized layered QC-LDPC decoder for IEEE 802.11ad,” 2013 IEEE 11th International New Circuits and Systems Conference (NEW- CAS), Jun. 2013, pp. 1–4.
[33] S. Ajaz and H. Lee, “Reduced-complexity local switch based multi-mode QC-LDPC decoder architecture for Gbit wireless communication,” Elec-

tronics Letters, vol. 49, no. 19, pp. 1246–1248, Sep. 2013.

[34] M. Li, J. W. Weijers, V. Derudder, I. Vos, M. Rykunov, S. Dupont,

P. Debacker, A. Dewilde, Y. Huang, L. V. der Perre, and W. V. Thillo, “An energy efficient 18 Gbps LDPC decoding processor for 802.11ad in 28nm CMOS,” in 2015 IEEE Asian Solid-State Circuits Conference (A- SSCC), Nov. 2015, pp. 1–5.
[35] M. Weiner, M. Blagojevic, S. Skotnikov, A. Burg, P. Flatresse, and

B. Nikolic, “A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI,” in 2014 IEEE In- ternational Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2014, pp. 464–465.
[36] L. Barnault and D. Declercq, “Fast decoding algorithm for LDPC over GF(2q),” in Proceedings 2003 IEEE Information Theory Workshop (Cat. No.03EX674), Mar. 2003, pp. 70–73.
[37] H. Wymeersch, H. Steendam, and M. Moeneclaey, “Log-domain decoding of LDPC codes over GF(q),” in 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577), vol. 2, Jun. 2004, pp. 772– 776 Vol.2.

[38] Y. L. Ueng, K. H. Liao, H. C. Chou, and C. J. Yang, “A high-throughput trellis-based layered decoding architecture for non-binary LDPC codes

using Max-log-QSPA,” IEEE Transactions on Signal Processing, vol. 61, no. 11, pp. 2940–2951, Jun. 2013.
[39] X. Chen and C. L. Wang, “High-throughput efficient non-binary LDPC decoder based on the simplified Min-Sum algorithm,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 11, pp. 2784–2794, Nov. 2012.
[40] D. Declercq and M. Fossorier, “Decoding algorithms for nonbinary LDPC codes over GF(q),” IEEE Transactions on Communications, vol. 55, no. 4, pp. 633–643, Apr. 2007.
[41] V. Savin, “Min-Max decoding for non binary LDPC codes,” in 2008 IEEE International Symposium on Information Theory, Jul. 2008, pp. 960–964.
[42] E. Li, D. Declercq, and K. Gunnam, “Trellis-based extended Min-Sum algorithm for non-binary LDPC codes and its hardware structure,” IEEE Transactions on Communications, vol. 61, no. 7, pp. 2600–2611, Jul. 2013.
[43] J. O. Lacruz, F. Garca-Herrero, D. Declercq, and J. Valls, “Simplified trellis Min-Max decoder architecture for nonbinary low-density parity- check codes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1783–1792, Sep. 2015.
[44] J. O. Lacruz, F. Garca-Herrero, J. Valls, and D. Declercq, “One minimum only trellis decoder for non-binary low-density parity-check codes,” IEEE

Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 177–184, Jan. 2015.
[45] J. O. Lacruz, F. Garca-Herrero, and J. Valls, “Reduction of complexity for nonbinary LDPC decoders with compressed messages,” IEEE Trans- actions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2676–2679, Nov. 2015.
[46] H. P. Thi and H. Lee, “Two-extra-column trellis Min-Max decoder archi- tecture for nonbinary LDPC codes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 5, pp. 1787–1791, May 2017.
[47] J. O. Lacruz, F. Garca-Herrero, M. J. Canet, and J. Valls, “Reduced- complexity nonbinary LDPC decoder for high-order Galois fields based on trellis Min-Max algorithm,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 8, pp. 2643–2653, Aug. 2016.
[48] B. Zhou, J. Kang, S. W. Song, S. Lin, K. Abdel-Ghaffar, and M. Xu, “Construction of non-binary quasi-cyclic LDPC codes by arrays and array dispersions,” IEEE Transactions on Communications, vol. 57, no. 6, pp. 1652–1662, Jun. 2009.
[49] H. P. Thi and H. Lee, “Basic-set trellis Min-Max decoder architecture for nonbinary LDPC codes with high-order Galois fields,” IEEE Transactions

on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 496– 507, Mar. 2018.
[50] X. Zhang and F. Cai, “Efficient partial-parallel decoder architecture for quasi-cyclic nonbinary LDPC codes,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 2, pp. 402–414, Feb. 2011.
[51] J. O. Lacruz, F. Garca-Herrero, M. J. Canet, and J. Valls, “High- performance NB-LDPC decoder with reduction of message exchange,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1950–1961, May 2016.
[52] M.-R. Li, C.-H. Yang and Y.-L. Ueng, “A 5.28-Gb/s LDPC decoder With time-domain signal processing for IEEE 802.15.3c applications,” IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 592-604, Feb. 2017.
[53] M.-R. Li, W.-X. Chu, H.-J. Huang, and Y.-L. Ueng, “An Eefficient non- binary LDPC decoder architecture with early termination using a modi- fied trellis Min-Max algorithm,” IEEE Transactions on Circuits and Sys- tems I: Regular Papers, submitted.