類似電路交換機之封包延遲控制的容量預留演算法

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研究生：	謝旻錡 Min-Chi Hsieh
論文名稱：	類似電路交換機之封包延遲控制的容量預留演算法 Capacity Reservation Algorithm for Packet Delay Control on Quasi-circuit Switches
指導教授：	蔡育仁 Ywh-Ren Tsai
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	57
中文關鍵詞：	交換機、類似電路交換機、高速交換機、封包延遲、服務品質、布可荷夫-范紐曼交換機
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由於科技的快速進步，人們對網路的需求越來越大，快速的傳輸設備變的重要。隨著光纖的出現，開始運用可調變傳輸速度的光纖來傳輸封包，於是高速封包交換機也隨之必要產生．
因為輸出阜有暫存器交換機 (Output-buffered switch) 受到記憶體存取速度的限制，其記憶體存取速度必須是輸入阜總數的兩倍以上，所以能夠平行處理資料讀與寫的交換機 -- 輸入阜有暫存器的交換機 (Input-buffered switch) 是大家近來研究主要的方向，但此架構會因為序列封包(head-of-line,HOL)阻塞而導致系統輸出量降低，以及控制封包延遲是相當困難的，接著 Birkhoff-von Neumann 交換機的出現，運用許多控制機制使得封包失序的現象可以解除．為了能夠控制封包延遲，類似電路交換機 (quasi-circuit switch) 在近來被提出，利用類似電路交換機可以達到服務品質保證．
原先的準線路式交換機是建構在輸入訊務符合峰值平穩 ((r, T)-smooth) 的限制條件之下，也就是在一定的時間區間之內，每一個流量的訊務量確保一定在某一個已知的最大訊務量之下。基於此種假設，只要交換機的最大流量預訂沒有超額，則可以確保在每一個碼框內的所有輸入封包，都可以順利的被交換機傳送到適當的輸出埠。然而由於輸入的訊務量受到峰值平穩的條件限制，將使得交換機的輸出效能低於 100%，特別是當輸入流量具有相當大的變異度時，整體交換機的效能將大為降低．於是在這篇論文中，我們運用一些容量預留演算法讓所有輸入阜的封包延遲能夠接近並且嘗試幾種不同的輸入阜流量，分析不同的容量預留演算法在不同的輸入阜流量時，各個輸入阜的表現．

As the technology becomes more and more mature, it is necessary to build up high-speed transmission equipment. People begin trying to use optical fiber to transmit data. For the reason, there is an urgent need to establish high speed switches so as to match the speed of optical fiber.
Because the shared medium switches (output-buffered switches) both have a major problem that is the scalability limitation, so the switch architecture permits read and write at the same time – the input-buffered switches gets a lot of attention. And then the Birkhoff-von Neumann switches is proposed, it uses some control stage to solve the out-of-sequence problem. In order to control pack delay, quasi-circuit switch is proposed.
When the input traffic pattern is not (r,T)-smooth, the performance of input ports is different, especially the last input port, it having the worst performance. In this thesis, we propose some capacity reservation for packet delay to let the performance of every input port be about the same. We look at the performance with different traffic pattern in simulation.

Contents

Abstract                            i

Contents                           ii

1 Introduction                                  1

2 Switch architecture                         3
   2.1 Basic Switch Architecture       …………………………3
   2.2 The Problem of Input-buffered Switch        ……………5
       2.2.1 HOL Blocking                 ………………………5
       2.2.2 Virtual Output Queueing (VOQ)         …………6
   2.3 Load balanced Birkoff-von Neumann Switches      ……7
       2.3.1 Birkhoff-von Neumann Switch        ……8
       2.3.2 Load Balanced Birkhoff-von Neumann Switches:
             One-stage Buffering              ………………9
       2.3.3 Load Balanced Birkhoff-von Neumann Switches:
             Multi-stage Buffering                 …………10
3 Quasi-circuit switch                     12
  3.1 The QoS and Control of Packet Delay   …………………12
  3.2 The Property of Quasi-circuit Switch        …………14
      3.2.1 (r,T)-smooth               …………………14
      3.2.2 The Detail Architecture of Quasi-Circuit
            switch                              ……………15
  3.3 Quasi-circuit Switch without (r,T)-smooth constrain 17
4 Capacity Reservation Algorithm for Packet Delay Control 19
  4.1 Impression             ………………………………………19
  4.2 Determination of Average Packet delay     ……………20
      4.2.1 Average delay of input port i       ……………20
      4.2.2 Ideal Difference of Queue Length    ……………23
  4.3 Control Algorithm – Algorithm 1 & 2  …………………24
      4.3.1 Algorithm - 1              …………………………24
      4.3.2 Algorithm - 2           ……………………………25
5 Simulation Results and Discussion                       27
  5.1 Basic Framework Simulation      …………………………27
      5.1.1 Average Delay of Overall Packets versus Input
            port                      …………………………27
      5.1.2 Simulation Results of Input-buffered Framework
                  ……………………………………………………28
  5.2 Simulation Results of Algorithm 1        …………30
  5.3 Simulation Results of Algorithm 2       ………………32
  5.4 Performance Comparison        ……………………………34
      5.4.1 Performance Comparison for Different Input Ports       ………………34
      5.4.2 Performance Comparison for Different Frame Size       ………………37
  5.5 Pareto Traffic Model                     ……………39
  5.6 Performance of Control Algorithms for Input Traffic
      with Large Variance                   …………………51
6 Conclusion                                 55

Bibliography                                      56

                                

Bibliography

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[4] D. Stiliadis and A. Varma, “Providing bandwidth guarantees in an input-buffered crossbar switch,” in Proc. IEEE INFOCOM, pp. 960-968, 1995.
[5] C.-S. Chang, W.-J. Chen and H.-Y. Huang, “Birkhoff-von Neumann input buffered crossbar switches,” in Proc. IEEE INFOCOM, pp. 1614-1623, 2000.
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[8] C.-S. Chang, D.-S. Lee and C.-M. Lien, “Load balanced Birkhoff-von Neumann switches, part I: multi-stage buffering,” Computer Communications, vol. 25, pp. 623-634, 2002.
[9] C.-S. Chang, D.-S. Lee, and C.-Y. Yue, “Providing Guaranteed Rate Services in the Load Balanced Birkhoff-von Neumann switches,” in Proc. IEEE INFOCOM, pp. 1622-1632, 2003.
[10] C.-S. Chang, and D.-S. Lee, “Quasi-circuit Switching and Quasi-circuit Switches.” to be presented in C.-S. Chang's home page.
[11] I. Keslassy, and N. McKeown, “Maintaining Packet Order in Two-Stage Switches,” Proc. IEEE INFOCOM, pp. 1032-1041, June 2002.
[12] I. Keslassy, S-T Chuang, and N. McKeown, “A Load-Balanced Switch with an Arbitrary Number of Linecards,” Proc. IEEE INFOCOM, pp. 2007- 2016, March 2004.
[13] N. McKeown, “The iSLIP Scheduling Algorithm for Input-Queued Switches,” IEEE Transactions on Networking, vol. 7, pp. 188-201, April 1999.

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