As transistors keep shrinking, the interconnect delay and power consumption become the bottleneck of the traditional two- dimensional integrated circuit. The three-dimensional integration is proposed to improve the existing 2D circuit by providing the benefits of shorter interconnect and lower power consumption. It integrates the multiple dies into a single stack and connects each dies by the Through-Silicon-Via (TSV). By the vertical connection (TSV), it can reduce the interconnect length significantly, but if the TSVs are ill-placed, the benefits of 3D IC would vanish. The 3D IC technology is currently being developed in an early stage. The size of TSVs is even larger than the standard cells, so we deal with signal-TSVs in the floorplan stage. In this paper, we propose an efficient fixed-outline signal-TSVs and modules co-floorplanner of 3D IC on a scalable face-to-back bonding structure. First, our tool read layer-assigned netlist. We simultaneously floorplan the circuit of each layer and do the wirelength optimization in the global layout stage. Second, we use the enumerative method to create the end-case layout and bottom-up combine the shape curve on each slicing nodes. Finally, we choose the layouts in the fixed-outline and optimize the wirelength of the 3D layouts. The experimental results show our method yields high-quality results and has excellent computational efficiency.

隨著超大型積體電路步入22奈米的階段，製造成本、良率、電路消耗功率、物理上的極限..等問題成為二維度積體電路的發展上的瓶頸。近年來，三維度積體電路的技術開始蓬勃發展且有效地解決傳統積體電路的各個瓶頸。三維度積體電路透過直通矽晶穿孔(TSV)的技術提高了電路效能(performance)、降低消耗功率(power consumption)、減少製造成本、增加單位面積的電晶體個數..等多項優點，替半導體產業注入一劑強心針。目前直通矽晶穿孔的製程仍然處於初期階段，在樓層規劃的階段中直通矽晶穿孔的面積仍然是不可被忽略。它位置會對效能、消耗功率、晶片溫度、良率(yield)..等因素造成極大的影響，本論文提供了兩套高效率三維度樓層規劃(3D IC floorplanner)軟體，在不同的積體電路設計階段(IC design flow)決定直通矽晶穿孔(TSV)和電路元件(modules)的位置，本實驗根據各種不同大小的直通矽晶穿孔，分別在樓層規劃階段中和樓層規劃階段後決定直通矽晶穿孔的位置，分析各種大小的直通矽晶穿孔分別適合在哪些階段來處理。

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Anne-Marie Corley, “Design Challenges Loom for 3-D Chips,” in Proc. of International Solid-State Circuits Conference, 2010.

Chang-Tzu Lin, D.M K, et al., “CAD Reference Flow for 3D via-Last Integrate Circuits,” in Proc. Asia and South Pacific Design Automation Conference, pp.187-192,
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Xiangyu Dong and Yuan Xie, “System-Level Cost Analysis and Design Exploration for Three-Dimensional Integrated Circuits (3D ICs),” in Proc. Asia and South Pacific Design Automation Conference, pages 234-241, 2009.

Ming-Chao Tsai, T.C Wang, T.T Hwang “Through-Silicon Via Planning in 3D floorplanning,” To be appeared on TVLSI.

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2008.

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GSRC floorplan benchmarks.
http://vlsicad.eecs.umich.edu/BK/GSRCbench/.

DeFer Source Code.
http://www.public.iastate.edu/zijunyan/

CS2: min-cost flow solver.
http://www.igsystems.com/cs2/index.html

hmetis: hypergraph partitioner.
http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview

HotSpot: thermal profile tool
http://lava.cs.virginia.edu/HotSpot/