鎖相迴路在通訊系統和電腦中扮演重要的角色，因為鎖相迴路是決定系統速度和效能的重要因素之一。在本文中，除了關注在抖動的分析外，還設計鎖定偵測器，偵測鎖相迴路是否已鎖定。在節能的議題上，我們設計了PDM的控制訊號，讓這類型的鎖相迴路在系統不需要的時候進入省電模式。
本論文的晶片使用SMIC 0.13μm 1P8M CMOS製程實現。在操作電壓為1.2V時，鎖相迴路中的電壓控制振盪器，其振盪頻率範圍是從500MHz到1GHz，並且有控制訊號可以改變除頻器的除數，因此鎖相迴路的輸出頻率範圍可以從62.5MHz到1GHz。在輸出頻率為960MHz時，最大峰對峰的抖動量和方均根的抖動量分別是105ps和13.39ps，此時晶片功率消耗為14.3mW。在省電模式時，供應核心電路的電源其功率消耗為0.516mW。核心電路是520um×460um。從模擬可以發現，鎖定偵測器偵測到的鎖定時間不超過7us。
從量測晶片的過程中，我們發現電源的雜訊和輸入參考訊號的抖動對鎖相迴路的輸出有很大的影響，因此對於鎖相迴路受到這些雜訊的干擾做了進一步的模擬和分析，特別是鎖相迴路中的相位頻率偵測器和電壓控制振盪器。這些影響產生的週期對週期之間的抖動，對於之後相連的數位電路很重要，因為過大的週期對週期的抖動容易造成數位系統出錯。除了模擬這些影響產生的量有多大之外，並建構方程式去預測最大週期對週期的抖動。

Phase-locked loop (PLL) plays an important role in communication and computer systems because PLL affects the speed and performance of the system. In this thesis, besides focusing on the analysis of jitter, lock detector circuit is designed to detect whether the PLL is locked or not; in the issue of energy saving, we design the control signal PDM (Power Down Mode) to turn off the PLL in power down mode when the system does not need it.
A PLL is implemented in SMIC 0.13μm 1P8M CMOS process. The output frequency range is from 62.5MHz to 1GHz at 1.2V supply voltage, while the oscillation frequency of voltage controlled oscillator is from 500MHz to 1GHz. Control signals are available to change the divisor of feedback frequency divider. The peak-to-peak jitter and RMS jitter of the PLL are 105ps and 13.39ps at 960MHz, respectively. The power consumption of the chip is 14.3mW at 960MHz and the core (1.2V supply) power consumption of core power is 0.516mW in power down mode. The area of core circuit is 520um×460um. From simulation, the locking time of the PLL is no more than 7us.
In the process of measuring the chip, we observed significant impacts of power and input phase noise on the output signal of the PLL. Therefore, we simulated and analyzed the PLL with noisy inputs, especially for the phase frequency detector (PFD) and the voltage controlled oscillator (VCO). These noises resulted in large cycle-to-cycle jitters which is critical to PLL’s applications. A large cycle-to-cycle jitter can cause the system to fail. As a result of our extensive simulation and analysis, we developed equations to predict the max cycle-to-cycle jitter.

[1]K. H. Cheng, T. H. Yao, S. Y. Jiang, W. B. Yang, “A Difference Detector PFD for Low Jitter PLL”, IEEE International Conference on Electronics, Circuits and Systems, vol. 1, pp. 43-46, 2001.
[2]M. Parvizi, A. Khodabakhsh, A. Nabavi A., “Low-Power High-Tuning Range CMOS Ring Oscillator VCOs,” ICSE2008, p. 40–44 (2008).
[3]Hai Qi Liu, Wang Ling Goh and Liter Siek," A 0.18-μm 10-GHz CMOS Ring Oscillator for Optical Transceivers," in IEEE Int. Symposium on Circuits and Systems, Vol. 2, pp. 1525-1528, May 2005
[4]J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE J. of Solid-State Circuits, vol. 35, pp. 1137-1145, Aug. 2000.
[5]F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” in IEEE Trans. Circuits Syst. II, vol. 46, pp. 56-62, Jan. 1999.
[6]J. A. McNeil and D. S. Ricketts, The Designer’s Guide to Jitter in Ring Oscillators. Springer, 2008.
[7]S. L. Liu and C. Y. Yang, Phase-Locked Loop. Tsang Hai, 2008.