摘要
TFT-LCD（thin film transistor-liquid crystal display）面板由薄膜電晶體（TFT Array）、面板組立（Cell）及模組（Module）三大製程所構成，其中以TFT Array製程為最重要。由於TFT Array製程為三段製程之首，且因製程時間最長、機台設備最為昂貴，成為TFT-LCD製程的瓶頸所在。TFT Array製程對整個生產鏈之產出有重要的影響，若未能達到生產規劃部門所制定的產出計畫，將使後續製程發生缺料的狀況。因此，如何有效控制製造現場之在製品分布狀況，便成為影響TFT-LCD生產鏈的關鍵因素。
TFT Array製程具有許多特性與限制，使其現場控制變得相當複雜。TFT Array製/程具有受限產能迴流的特性，再加上其中的瓶頸黃光製程除機台以外需搭配光罩才可加工，每種產品的各迴流層都有其專屬的光罩，且光罩與瓶頸機台之間有一特定的搭配限制。同時，因為光罩成本昂貴，製造現場擁有之光罩數量有限，使光罩成為現場控制需要考量的限制。在迴流、光罩與機台搭配關係及光罩數量限制的特性下，造成現場之產能隨搭配方式波動，本研究提出考量黃光機台前在製品分布狀況之動態光罩重配置方法，來解決現場因光罩配置造成之產能波動問題，並透過模擬分析與傳統迴流環境中所討論之投料、派工方法進行比較，探討何者對系統績效影響較為顯著。
藉由實驗設計與模擬分析發現，本研究所提出的光罩重配置方法，無論在何種生產條件下，皆可使現廠產能有效控制，並發現光罩配置對系統績效之影響遠大於投料與派工方法。

關鍵字：陣列廠、迴流、光罩、投料、副資源配置。

參考文獻
1. 林則孟，「系統模擬理論與應用」，滄海書局，2001。
2. 林則孟，「生產計畫與管理」，華泰文化，2006。
3. 陳亞妮，「薄膜電晶體陣列廠生產規劃系統之建構」，交通大學工業工程與管理所碩士論文，2004。
4. 顏如敏，「TFT Array廠在光罩限制下之現場排程問題」，國立清華大學工業工程與工程管理研究所碩士論文，2006。
5. 游淑晴，「黃光區關鍵層機台限制機台指派投料與派工法則探討」，國立清華大學工業工程與工程管理研究所碩士論文，2003。
6. 張永政，「半導體廠綁機情境下之投料與派工」，國立交通大學工業工程與管理學系碩士論文，2003。
7. 黎翠綾，「在機台群組限制下的黃光區投料派工模式」，國立交通大學工業工程與管理學系碩士論文，1999。
8. 簡秀安，「TFT-LCD產業陣列製程投料機制之建構與績效分析」，東海大學工業工程與經營資訊研究所碩士論文，2004。
9. Akcalt, E., Nemoto, K., and Uzsoy, R., “Cycle-Time Improvements for Photolithography Process in Semiconductor Manufacturing,” IEEE Transaction on Semiconductor Manufacturing, Vol. 14, No.1, pp. 48~56, 2001.
10. Blackstone, J. H., Phillips, D. T., and Hogg, G. L., “State-of-the-art Survey of Dispatching Rules for Manufactruing Job Shop Operation,” International Journal of Production Research, Vol. 20, pp. 27-45, 1982.
11. Garrett, V. R., Sheldon, X. C. L., and Stanley, B. G., “Production Control for A Tandem Two-Machine System,” IIE Transactions, Vol. 25, No.5, 1993.
12. Glassy, C. R. and Resende, M. G. C., “Closed-loop Job Release Control for VLSI Circuit Manufacturing”, IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, pp.26-48, 1988a.
13. Glassy, C. R. and Resende, M. G. C., “A Scheduling Rule for Job Release in Semiconductor Fabrication,” Operation Research Letters, Vo7. 5, No. 1, pp.213-217, 1988b.
14. Goldratt, E. M., “The Haystack Syndorme”, Croton-on-Hudson: North River, 1990.
15. Hwang, H., Sun, J. U., “Production Sequencing Problem with Reentrant Work Flows and Sequence Dependent Setup Times,” International Journal of Production Research, Vol.36, No. 9, pp. 2435~2450.
16. Kim, Y. D., Kim, J.U., Lim, S. K., “Due Date Based Scheduling and Control Policies in a Multi-Product Semiconductor Wafer Fabrication Facility,” IEEE Transaction on Semiconductor Manufacturing, Vol. 11, No.1, pp. 155~164, 1998a.
17. Kim, Y. D., Lee, D., Kim, J.U., “A Simulation Study on Lot Release Control , Mask Scheduling and Batch Scheduling in Semiconductor Wafer Fabrication Facility,” Journal of Manufacturing Systems, Vol. 17, No. 2, pp.107~117, 1998b.
18. Kumar, P. R. and Meyn, Sean P., “Stability of queueing networks and scheduling polices,” Proceedings of the IEEE Conference on Decision and Control, Vol. 3, pp. 2730~2735, 1993.
19. Kumar, R., Tiwariz, M. K., and Alladay, V., “Modeling and Rescheduling of a Re-entrant Wafer Fabrication Line Involving Machine Unreliability,” International Journal of Production Research, Vol.42, No. 21, pp. 4431~4455, 2004.
20. Lamba, N., Karimi, I. A., and Bhalla A., “Scheduling a Single-Product Reentrant Process with Uniform Processing Times,” Industry Engineering Chemistry Research, Vol. 39, pp. 4203~4214, 2000.
21. Lee, Y. H. and Lee, B., “Push-Pull Production Planning of The Re-entrant Process,” International Journal of Advanced Manufacturing Technology, Vol. 22, No. 11~12, pp. 922~931, 2003.
22. Lu, S. C., Ramaswamy, D. and Kumar, P. R., “Efficient Scheduling Policies to Redue Mean and Variance of Cycle Time in Semiconductor Plants,” IEEE Transaction on Semiconductor Manufacturing, Vol. 7, pp. 374~388, 1994.
23. Lou, S., and Kager, P. W., “A Robust Production Control Policy for VLSI Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 2, pp. 3-9, 1990.
24. Melnyk, S. A., and Ragatz, G. L., “Order Review/Release: Research Issues and Perspectives,” Inyrtnsyion Joutnsl of Production Research, Vol 27, pp.1081~1096, 1989.
25. Miragliotta, G. and Perona, M., “Decentralised, Multi-Objective Driven Scheduling for Reentrant Shops: A Conceptual Development and A test Case”, European Journal of Operational Research, Vol. 167, No.3, pp.644-662, 2005.
26. Nose, K., Hiramatsu, A., and Konishi, M., “Using Genetic Algorithm for Job-Shop Scheduling Problems with Reentrant Product Flows,” IEEE Symposium on Emerging Technologies and Factory Automation, ETFA, Vol. 2, pp. 1339~1346, 1999.
27. Pearn, W. L., Chung, S. H., Chen, A. Y., and Yang, M. H, “A case study on the multistage IC final testing scheduling problem with reentry,” International Journal of Production Economics, Vol. 88, No.3, pp. 257~267, 2004.
28. Schragenheim, E. and Renen, B., “Drum-buffer-rope Shop Floor Control,” Production and Inventory Management Journal, 3rd Quarter, Vol. 31, No. 3, pp.18~23, 1990.
29. Schragenheim, E. and Renen, B., “Buffer Management. A Diagnostic Tool for Production Control,” Production and Inventory Management Journal, 2nd Quarter, Vol. 32, No. 2, pp.74~79, 1991.
30. Spearman, M. L., Woodruff, D. L., and Hopp, W. J., “CONWIP: A Pull Alternative to Kanban,” International Journal of Production Research, Vol. 28, No. 5, pp. 879-894, 1990.
31. Uzsoy, R., Church, L., Ovacik, I., “Performance Evaluation of Dispatching Rules for Semiconductor Testing Operations,” Journal of Electronics Manufacturing, Vol. 3, pp. 95~105, 1993.
32. Uzsoy, R., Lee, C., Martin Vega, L., “A Review of Production Planning and Scheduling Models in the Semiconductor Industry, Part 1: System Characteristics, Performances Evaluation and Production Planning,” IIE Transaction, Vol. 24, pp.47~60, 1992.
33. Vargas-Villamil, F. D., and Rivera, D. E., “Multilayer Optimization and Scheduling Using Model Predictive Control: Application to Reentrant Semiconductor Manufacturing,” Computers and Chemical Engineering, Vol. 24, pp. 2009~2021, 2000.
34. Yura, K., “Cyclic Scheduling for Re-entrant Manufacturing Systems,” International Journal of Production Economics, Vol. 60-61, pp. 523~528, 1999.
35. Wein, L. M., “Scheduling Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, pp.115-130, 1988.
36. Wu, H. H. and Yeh, M.L., "A DBR Scheduling Method for Manufacturing Environments with Bottleneck Reentrant Flows," International Journal of Production Research, Vol. 44, No. 5, pp. 883-902, 2006.
37. Wu, S. Y., Morris J. S., and Gordon T. M., “A Simulation Analysis of the Effectiveness of Drum-Buffer-Rope Scheduling in Furniture Manufacturing,” Computers and Engineering, Vol. 26, No. 4, pp. 757-764, 1994.
38. Yan H., Lou, SXC, Sethi SP, Gardel A., and Deosthali P., “Testing the Robustness of Various Production Control Policies in Semiconductor Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 2, pp. 285-289, 1996.