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研究生：	姚柏佑 Yao, Bo-You
論文名稱：	商用現貨嵌入式系統模擬框架 Generic Simulation Framework for COTS Embedded System Design
指導教授：	周百祥 Chou, Pai H.
口試委員:	韓永楷 Hon, Wing-Kai 謝孫源 Hsieh, Sun-Yuan 李皇辰 Lee, Huang-Chen
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2024
畢業學年度：	112
語文別：	英文
論文頁數：	39
中文關鍵詞：	模擬、嵌入式、慣性感測器、功能模擬、功能設置、離散事件模擬
外文關鍵詞：	simulation, COTS, embedded, IMU, functional simulation, discrete event simulation
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本論文提出了一個適用於Sysmaker的模擬框架，Sysmaker是一個用於設計基於商用現貨（COTS）嵌入式系統的工具。基於在Sysmaker中創建的電路板級（Board-Level）設計，我們的模擬框架整合了不同的模擬模型，其中包括指令集模擬器（ISS）、感測器和致動器等週邊裝置，以及一個環境模型。環境模型提供目標環境的數值以驅動模擬，並收集元件輸出，以便手動或自動檢查設計正確性。這項工作的挑戰主要在於如何在商用現貨元件之間平衡模擬效率和可觀察細節的程度，同時解決這些模擬模型之間關於時序和事件的不同假設，通常需要進行一定程度的逆向工程。另一個挑戰在於感測器等週邊裝置的資料來源，這些資料最終必須來自環境，並且必須在所有會被這些事件影響的裝置之間做同步。

我們提出的模擬框架允許設計人員選擇所需的抽象等級來進行模擬，目前支持邏輯層（logic-level）和資料交換層（transaction-level）的資料傳輸方式，允許靈活地模擬元件之間的資料傳輸。在構建（elaboration）階段，我們的框架提取相應的模擬模型，並生成模擬所需的程式碼。在編譯階段，這些模型被編譯並鏈結成一個可執行檔案，用於模擬目標系統及目標環境。用戶可以通過環境模型提供輸入或者連接一個物理模擬器作為目標環境的資料來源。我們的框架基於SystemC，它整合了RISC-V VP指令集架構模擬器、為MPU-9250慣性測量裝置（IMU）自行設計的模擬模型及其通訊界面、用於發出硬體命令的裝置暫存器，以及與環境的通訊界面。

最終結果證明了我們的方法在捕捉特定元件行為和實現設計空間探索（design space exploration）方面的有效性。可以捕捉到週邊裝置中的暫存區溢出（overflow）和下溢（underflow）等錯誤，這些錯誤無法使用任何除錯器或現有模擬器檢測出來。本論文為基於商用現貨嵌入式系統的設計和驗證提供了一個寶貴的工具，解決了現有方法的局限性，並為模擬複雜的嵌入式系統提供了一個靈活、高效的模擬平臺。

This thesis proposes a simulation framework for Sysmaker, a design tool for COTS-based embedded systems. Based on a board-level design created in Sysmaker, our simulation framework assembles the simulation models, which may include an instruction-set simulator (ISS), peripheral devices such as sensors and actuators, and an environment model that provides the input to drive the simulation as well as collecting the output for manual or automatic checking of correctness. What makes this work challenging is how to balance simulation efficiency with the level of observable detail among the COTS components, while resolving the diverse assumptions about timing and events of these simulation models, which often need to be reverse-engineered to some extent. Another challenge is with the data source of the peripheral devices such as sensors, which must be ultimately derived from the environment and be synchronized among all devices sensitive to those events.

Our proposed simulation framework allows designers to choose the desired level of abstraction at which to simulate, and it currently supports both logic-level and transaction-level communication, allowing for flexible and efficient simulation of the interactions between components. During the elaboration phase, our framework extracts the corresponding models and generates the necessary code for their integration. During the compilation phase, these models are translated and linked into an executable for the simulator of the target design and its environment. The user can provide input through the environment model or connect a physical world simulator as a data source for the target system.
Our prototype is based on SystemC, which integrates the RISC-V Virtual Prototype (VP) instruction set simulator, our own model of the MPU-9250 inertial measurement unit (IMU) with its bus interface, its device registers for issuing hardware commands, and its interface to the environment.

The results demonstrate the effectiveness of our approach in capturing component-specific behaviors and enabling design space exploration. It can catch bugs such as buffer overflow and underflow conditions in peripheral devices, which otherwise cannot be detected using any debuggers or existing simulators.
This thesis contributes a valuable tool for the design and validation of COTS-based embedded systems, addressing the limitations of existing approaches and providing a flexible, efficient, and accurate platform for simulating complex embedded systems.

Contents
Contents i
Acknowledgments vi
Introduction                                                     1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 System Testing . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Option: Evaluation Boards . . . . . . . . . . . . . . . . . .2
1.3 Option: Simulation . . . . . . . . . . . . . . . . . . . . . 2
1.4 Test Data . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . .3
3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . .4
Related Work                                                     5
1 System-Level Design and Description Languages . . . . . . . . .5
2 Simulation Framework . . . . . . . . . . . . . . . . . . . . . 6
2.1 Modelica . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Ptolemy . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.3 OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.4 SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Cycle-Accurate Simulators . . . . . . . . . . . . . . . . . . .7
4 Prototyping and Simulation Platforms . . . . . . . . . . . . . 8
Methodology                                                      9
1 The Sysmaker Design Framework . . . . . . . . . . . . . . . . .9
i
1.1 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Design Refinement and Validation . . . . . . . . . . . . . . 10
2 SimBuilder . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Input - Design . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Input - Environment . . . . . . . . . . . . . . . . . . . . .12
2.3 Input - Configuration File . . . . . . . . . . . . . . . . . 13
2.4 Multi-Level Communication . . . . . . . . . . . . . . . . . .13
2.5 Issue Detection and Logging . . . . . . . . . . . . . . . . .14
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Technical Approach                                               16
1 Key Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1 Multi-Level Communication . . . . . . . . . . . . . . . . . .16
1.2 Simulation Unit . . . . . . . . . . . . . . . . . . . . . . .17
2 SimBuilder Overview . . . . . . . . . . . . . . . . . . . . . .19
3 Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . .19
4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Simulation Loop . . . . . . . . . . . . . . . . . . . . . . .26
4.3 Termination . . . . . . . . . . . . . . . . . . . . . . . . .26
5 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Implementations                                                  28
1 Communication Tunnel . . . . . . . . . . . . . . . . . . . . . 28
2 RISC-V VP . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3 Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . .30
4 Record File Format . . . . . . . . . . . . . . . . . . . . . . 30
Case Study                                                       32
1 System Description . . . . . . . . . . . . . . . . . . . . . . 32
2 Target Environment . . . . . . . . . . . . . . . . . . . . . . 33
3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ii
4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Conclusions and Future Work                                      37
                                

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