隨著電子產品微小化的趨勢，產品中的電源供應系統也朝著縮小設計面積與移除被動元件的方向前進，有兩種主要方式以達到這兩個個方向，分別是提高轉換頻率與數位化實現電路。在電源供應系統中切換式降壓轉換器在轉換電壓時可以擁有比線性穩壓器更高的效率，其中對於轉換頻率的限制則發生在數位脈波寬度調變器中，因為傳統的設技方式在設計高轉換頻率時會有面臨到面積與功率上的問題。
數位脈波寬度調變器傳統上有兩種設計方式，分為 (1) Counter based (2) Delay-Line based；其中第一種架構是使用高頻率的脈波去組合出想要的脈波寬度，而第二種則是以選取延遲鎖相迴路的相位來產生脈波寬度。但是使用第一種架構必須要操作在比切換頻率更高速的時脈，在高速操作下會需要較大的功率。使用第二種方式設計在設計足夠的解析度情況下延遲鎖相回路會需要較大的面積且功率的消耗也不能被接受。
為了降低操作在高階換頻率時所需要的功率，這個論文提出了使用雙層架構來設計數位脈波寬度調變器，並在內部設計了動態重置系統的電路以降低不必要的功率消耗。另外傳統的校正方式是使用電荷幫浦來調整延遲時間，此校正方式需要一個大面積的低通濾波器。為了減小面積在這個論文裡提出了一個數位校正的方式來實現校正電路。
　　這個論文提出的數位脈波寬度調變器可以運作在5MHz切換頻率並擁有10位元的解析度且功率與面積可以小於1.5mW與0.12mm2。另外設計了一個切換式降壓轉換器的模型以驗證提出的數位脈波寬度調變器可以應用在高切換頻的切換式降壓轉換器中。

In this thesis a 5 MHz, 10-bit resolution digital pulse width (DPWM) modulator is proposed. The 5 MHz switching frequency can effectively reduce filter size of switching-type DC-DC converter and decrease response time. 10-bit resolution is required in high accurate switching-type DC-DC converter to avoid limit cycle oscillation. A two-layer structure and dynamic reset scheme are proposed to decrease power consumption. The two-layer structure uses two different discharging current to generate desired delay. Dynamic reset scheme is reset system when output pulse-width has been generated. This scheme can reduce wasted
power after output pulse-width has been generated. A digital calibration approach is proposed to remove filter used in charge pump scheme. A switching-type DC-DC converter is constructed to demonstrate the proposed
DPWM can operate well when it integrated into the converter. A MATLAB simulation platform is designed to fast estimate the response of switching-type DC-DC converter. It shows the proposed DPWM can operate in 8 bit switching-type DC-DC converter without limit cycle oscillation.

[1] Y. Fukuda, T. Inoue, T. Mizoguchi, S. Yatabe, and Y. Tachi, “Planar inductor with ferrite layers for DC-DC converter,” IEEE Trans. Magn., vol. 39, Part 2, July 2003, pp 2057–2061.
[2] He. Mingzhi, and Xu. Jianping, “Nonlinear PID in Digital Controlled Buck Converters,”IEEE Applied Power Electronics Conference (APEC), pp. 1461–1465, Feb. 2007.
[3] B. Miao, R. Zane, and D. Maksimovic, “Automated Digital Controller Design for Switching Converters,” IEEE Power Electronics Specialists Conference (PESC), 2005, pp. 2729–2735
[4] P. Athalye, D. Maksimovic, and R. Erickson, “ Variable-frequency predictive digital current mode control,” IEEE Power Electronics Letters, vol. 2, pp. 113–116, Dec. 2004.
[5] G. Feng, W. Eberle, and Y. Liu , “A New Digital Control Algorithm to Achieve Optimal Dynamic Performance in DC-to-DC Converters,” IEEE Power Electronics Specialists
Conference (PESC), 2005, pp. 2744–2749
[6] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital pulse width modulator architectures,” IEEE Power Electronics Specialists Conference (PESC), vol. 6, pp. 4689–4695, June 2004.
[7] E. O’Malley, and K. Rinne, “A programmable digital pulse width modulator providing versatile pulse patterns and supporting switching frequencies beyond 15 MHz,” IEEE
Applied Power Electronics Conference and Exposition, vol. 1, pp. 53–59, 2004.
[8] B.J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converters,” IEEE Power Electronics, vol. 18, Part 2, pp. 438–446, Jan. 2003.
[9] A.V. Peterchev, and S.R. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters,” IEEE PESC, vol. 2, pp. 465–471, June 2001.
[10] V. Yousefzadeh, T. Takayama, and D. Maksimovi, “Hybrid DPWM with Digital Delay-Locked Loop,” IEEE Computers in Power Electronics , pp. 142–148, July 2006.
[11] R. W. Erickson, and D. Maksimovic, “Fundamentals of Power Electronics,” New York:Springer,Second Edition, 2004.
[12] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, “A 4 uA Quiescent-Current Dual-Mode Buck Converter IC for Cellular Phone Applications,” Digest IEEE Internat. Solid-
State Circ. Conf., vol. 47, pp. 280–281, 2004.
[13] A. Dancy, and A. P. Chandrakasan, “Ultra low Power Control Circuits for PWM Converters,”IEEE Power Electronics Specialist Conference, pp. 21–27, 1997.
[14] G. K. Schoneman, and D. M. Mitchell, “Output impedance considerations for switching regulators with current-injected control,” in Proc. IEEE PESC, 1987, pp. 324–335.
[15] Chen ingquan, M. Ribeiro, R. Payseo, Zhou Dongsheng, J.R. Smith, and K. Kernahan,“DPWM time resolution requirements for digitally controlled DC-DC converters,” IEEE Applied Power Electronics Conference and Exposition, pp. 6, March 2006.
[16] R.F. Foley, R.C Kavanagh, W.P Marnane, and M.G. Egan, “ A Versatile Digital Pulsewidth Modulation Architecture with Area-Efficient FPGA Implementation,” in IEEE Power Electronics Specialists Conference (PESC), pp. 2609–2619, 2005.
[17] Z. Lukic, Wang Kun, and P. Prodic, “ High-frequency digital controller for dc-dc converters based on multi-bit /spl Sigma/-/spl Delta/ pulse-width modulation,” Applied Power Electronics Conference and Exposition, vol. 1, pp. 35–40, March 2005.
[18] Peng Li, Kong Xuejuan, Kang Yong, and Chen Jian, “ A novel PWMtechnique in digital control and its application to an improved DC/DC converter,” IEEE Power Electronics
Specialists Conference, vol. 1, pp. 254–259, June 2001.
[19] S. Bibian, and H. Jin, “Time delay compensation of digital control for dc switch mode power supplies using prediction techniques,” IEEE Trans. Power Electron, vol. 15, pp. 835–842, Sept. 2000.
[20] K. Yao, Y. Meng, and F.C. Lee, “Control bandwidth and transient response of buck converters,” inProc. IEEE PESC, pp. 137–142, 2002.
[21] Ka Leung, and Alfano, D. “Design and implementation of a practical digital PWM controller,”IEEE Applied Power Electronics Conference and Exposition, 6 pp., March 2006.
[22] Hu Haitoa, V. Yousefzadeh, and D. Maksimovic, “Nonlinear Control for Improved Dynamic Response of Digitally Controlled DC-DC Converters,” IEEE Power Electronics Specialists Conference, pp. 1–7, June 2006.