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研究生： 陳奕廷
Chen, Yi-Ting
論文名稱： 10位元200Ms/s 低功率脈管式類比數位轉換器
A low power 10bit 200Ms/s Pipelined ADC
指導教授： 徐永珍
Hsu, Yung-Jane
口試委員: 郭明清
Kuo, Ming-Ching
黃吉成
Huang, Ji-Chen
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2018
畢業學年度： 106
語文別： 中文
論文頁數： 82
中文關鍵詞： 脈管式類比數位轉換器 、低功率 、類比數位轉換器
外文關鍵詞： Pipelined ADC, low power, analog-to-digital converter
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    • 隨著製程不斷進步，數位電路在運算處理能力與操作速度上發展迅速，並且能夠儲存大量的數位資訊，許多類比電路已逐漸改由位數電路的方式呈現，但是即使如此，電路與外界傳遞或接收資訊還是必須透過類比數位轉換器與數位類比轉換器來實現。為了實現低功率消耗且高速資料傳輸的電路，本研究使用包含前景式數位校正電路、Virtual Ground Reference Buffer、Switch Boostrapped…等等電路設計技巧來實現每秒取樣兩億次十位元脈管式類比數位轉換器，使的電路能夠在低功率消耗的情況下讓效能提高，以符合電子電路發展趨勢。

    類比數位轉換器特性在輸入全擺幅正弦波，頻率為4.5 MHz 正弦波模擬結果能得到為雜訊位準-85 dB，訊號對雜訊及失真比61.6 dB。在供應電壓源為1.8伏特時所消耗的功率為68.5mW，另外，在輸入全擺幅正弦波，頻率為10 MHz 正弦波量測結果能得到為雜訊位準-40 dB，訊號對雜訊及失真比24.8 dB。晶片面積含I/O Pads 約為2.52 mm2，並採用TSMC 0.18μm 1P6M Standard CMOS製程加以實現並封裝。

    A 10-bit 200-MS/s pipelined analog-to-digital converter (ADC) using virtual ground reference buffer and foreground calibration technique in TSMC 0.18μm standard CMOS process technology is presented.

    The simulated ADC performances achieve -85 dB of Noise Level , 61.6dB of SNDR for 4.5MHz input signal. Under 1.8-V supply, the power consumption of the proposed ADC is 68.5-mW. The measured ADC performances achieve -40 dB of Noise Level, 24.8 dB of SNDR for 10MHz input signal. The chip area including I/O pads is 2.52 mm2.

    摘要.............................................................1 Abstract.........................................................2 目錄.............................................................4 圖目錄...........................................................6 表目錄...........................................................9 第一章 前言.....................................................10 1.1 研究動機.................................................10 1.2 論文章節架構.............................................11 第二章 類比數位轉換器架構概論....................................12 2.1 類比數位轉換器的基本參數..................................12 2.2 類比數位轉換器架構介紹....................................15 2.2.1 快閃式類比數位轉換器......................................15 2.2.2 兩階式類比數位轉換器......................................17 2.2.3 脈管式類比數位轉換器......................................19 第三章 電路設計概論.............................................22 3.1 參考電壓緩衝器(Virtual Ground Reference Buffer)...........22 3.1.1 開迴路增益（open-loop-gain）..............................22 3.1.2 頻寬（bandwidth）........................................24 3.1.3 參考電壓緩衝器(Virtual Ground Reference Buffer)技術[2]....26 3.2 類比開關與其非理想效應....................................28 3.2.1 通道電荷注入（Charge injection）..........................28 3.2.2 時序饋入（Clock Feedthrough）............................29 3.2.3 開關阻值變化.............................................29 3.3 數位修正電路原理..........................................31 3.4 前景式數位校正電路原理....................................36 第四章 子電路分析與實現..........................................39 4.1 單級處理2.5位元之電路架構.................................39 4.2 Hybrid Cascode Compensation雙級放大器[6].................44 4.3 參考電壓緩衝器電路........................................51 4.4 比較器...................................................53 4.5 非重疊時序產生電路........................................58 4.6 偏壓電路.................................................59 4.7 脈管式類比數位轉換器整體效能模擬結果........................61 4.7.1 動態參數測試.............................................61 4.7.2 靜態參數測試.............................................66 4.7.3 模擬結果與文獻比較........................................67 第五章 晶片佈局與量測結果........................................68 5.1 晶片佈局.................................................68 5.2 量測環境.................................................71 5.3 量測結果.................................................72 5.4 分析與討論...............................................74 第六章 結論與未來展望...........................................78 6.1 結論....................................................78 6.2 後續研究建議.............................................79 參考文獻.........................................................81

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