隨著時脈頻率的增加，超導快速單磁通量子電路之時脈要求對於實現正確的電路功能極為重要。為滿足此要求，必須將長度匹配之條件納入繞線問題中。然而，現有繞線方法本質上是受限的，受限於預先配置的分離器，這使後續的繞線在長度匹配的限制下，變得更加複雜化。因此，在本論文中，我們透過重新配置分離器，將可以充分利用繞線資源，並有效地應對長度匹配問題。我們提出了第一個對於此電路之多端點的繞線演算法，將分離器的配置問題整合到繞線階段處理。由實驗結果證實，在實際電路上，我們提出的演算法可以完成繞線，同時減少17％所需面積。與過去的方法[1]相比，儘管在分離器預先配置的情況下，我們可以仍可以取得7％的改善。

With the increasing clock frequencies, the timing requirement of Rapid Single Flux Quantum (RSFQ) digital circuits is critical for achieving the correct functionality. To meet this requirement, it is necessary to incorporate length-matching constraint into routing problem. However, the solutions of existing routing algorithms are inherently limited by pre-allocated splitters (SPLs), which complicates the subsequent routing stage under length-matching constraint. Hence, in this thesis, we reallocate SPLs to fully utilize routing resources to cope with length-matching effectively. We propose the first multi-terminal routing algorithm for RSFQ circuits that integrates SPL reallocation into the routing stage. The experimental results on a practical circuit show that our proposed algorithm achieves routing completion while reducing the required area by 17\%. Comparing to [1], we can still improve by 7\% with less runtime when SPLs are pre-allocated.

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