研究生: |
吳哲逸 Wu, Che-Yi |
---|---|
論文名稱: |
一個具有校準功能並用高效能硬體實行的FD-OCT 成像應用設計 A Hardware-Efficient Design for Calibration-Enabled FD-OCT Imaging Applications |
指導教授: |
張慶元
Chang, Tsin-Yuan |
口試委員: |
張慶元
陳竹一 陳元賀 湯松年 |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 63 |
中文關鍵詞: | 光學斷層掃描 、頻率-光學斷層掃描 、快速傅立葉轉換 、座標軸數位旋轉計算器 、校準 |
外文關鍵詞: | OCT, FD-OCT, FFT, CORDIC, Calibration |
相關次數: | 點閱:2 下載:0 |
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OCT(Optical Coherence Tomography)系統是一種醫療式影像成像的系統,主要應用在表面的檢測,其優點在於對人體沒有副作用。OCT系統主要分為TD(Time Domain)以及FD(Frequency Domain)兩種。本篇論文主要使用FD-OCT的系統架構,系統架構主要分為重新取樣單元、漢明視窗單元、傅立葉以及逆傅立葉轉換單元以及Log單元。重新取樣單元利用校準參數重新取樣;漢明視窗單元降低資料因為不連續而產生的高頻雜訊;傅立葉以及逆傅立葉轉換單元使用硬體成本較低的SDF(single-path delay feedback)-Pipeline架構,並且以Radix-2^3以及Radix-2^4為基底來拆解DFT,其中再以CSD(Canonic Signed Digit)常數乘法器以及CORDIC(Coordinate Rotation Digital Computer)乘法器改良來降低成本花費;影像處理的Log運算以自然對數為底以及泰勒展開式來實現。為了支援校準功能的相位取得,利用CORDIC電路將相位求得;為了節省設計成本,將求相位的電路和傅立葉以及逆傅立葉轉換單元中的CORDIC電路合併共用。此外,相位的求得方式還必須經由傅立葉轉換、逆傅立葉轉換,因此使用控制電路多次路徑的重複使用傅立葉轉換的硬體來完成,並共用原有記憶體RAM來重新排序因傅立葉轉換架構而輸出位元反轉的資料順序以及等候傅立葉轉換架構運算完再次輸入使用逆傅立葉轉換運算,藉以達到多次路徑使用來達到降低硬體成本,經由共用CORDIC電路共節省了5.68%的硬體使用;經電路合成以及APR(Automatic Place and Route)後,操作頻率可以達到80MHz,系統硬體面積使用為503.7K gate counts。
OCT (Optical Coherence Tomography) imaging system is a kind of medical imaging system that is mainly applied in surface detection, with the main advantage of no side effects on the human body. OCT system can be roughly divided into TD(Time Domain) and FD(Frequency Domain). Using the FD-OCT system, the proposed system architecture consists of Re-sampling unit, Hamming window unit, Fourier and inverse Fourier transform unit, and Log unit. The Re-sampling unit applies the calibration parameters to do the re-sampling; the hamming window unit reduces the high frequency noise from un-continuous data; the Fourier and inverse Fourier transform unit use the SDF (single-path delay feedback)-Pipeline architecture, which is a lower-cost hardware architecture, CSD(Canonic Signed Digit) constant multiplier and CORDIC to save the cost and disassembles DFT by Radix-2^3 and Radix-2^4 algorithms; and Image Processing Log computes the natural logarithm base and Taylor expansion. To support the main phase of the calibration function obtained, the CORDIC circuit is applied to obtain the phase. In order to save design costs, the CORDIC multiplier and the phase obtaining circuit are shared. In addition, since the phase obtained method needs the Fourier transform and the inverse Fourier transform operations, the control circuit is applied for reusing the Fourier transform hardware, for sharing the original memory RAM to reorder data out, and to wait until the previous operation is completed. The shared CORDIC circuit saves 5.68% of the hardware in gate counts. After circuit synthesis and Automatic Place and Route, the operating frequency can be operated at 80MHz, and the use of system hardware area is 503.7K gate counts.
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