使用平行向量模擬來診斷大型組合電路之多重設計錯誤

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研究生：	蕭育霖 Yu-Lin Hsiao
論文名稱：	使用平行向量模擬來診斷大型組合電路之多重設計錯誤 Multiple Error Diagnosis in Large Combinational Circuits Using an Efficient Parallel Vector Simulation
指導教授：	王俊堯 Chun-Yao Wang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	37
中文關鍵詞：	診斷、設計錯誤、平行、向量、模擬
外文關鍵詞：	Diagnosis, Error, Parallel, Vector, Simulation
相關次數：	點閱：2 下載：0
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本篇論文提出以平行向量模擬為基礎的方法來找出大型組合電路之多重設計錯誤，我們提出兩種啟發式方法以避免錯誤空間的劇增，我們的實驗使用一系列ISCAS'85 和兩個大型電路的測資，實驗結果指出我們的方法能有效率地識別出少量可修改的線路，這些線路包括了真正出錯的來源，使得錯誤的組合電路能夠進一步地被修正回來

This paper presents a parallel vector simulation-based approach to locating multiple errors in large combinational circuits. Two heuristics are proposed to avoid the explosion of the error space. Experimental results on a set of ISCAS'85 and two large benchmarks show that our approach efficiently identifies a small set of correctable nodes that contains the actual error sources. Thus, further error correction can be conducted on the erroneous implementation.

Contents

摘 要...............................................i
ABSTRACT...........................................ii
Acknowledgements..................................iii
Contents...........................................iv
List of Tables......................................v
List of Figures....................................vi
Chapter 1. Introduction.............................1
Chapter 2. Preliminaries ...........................5
Chapter 3. Diagnosis Approach.......................9
3.1. Sensitization Set Derivation...................9
    3.1.1 Critical Path Tracing....................10
    3.1.2 PPSFP....................................13
3.2. Single Error..................................14
3.3. Multiple Errors...............................17
3.4 Overall Approach...............................24
Chapter 4. Experimental Results....................26
Chapter 5. Conclusion..............................34
References.........................................35

List of Tables

Table I. Experimental results on single error diagnosis...30
Table II. Experimental results on two-error diagnosis.....31
Table III. Performance speedup ratio with Heuristic 2.....32
Table IV. Comparison of our results with Huang’s [3] and Veneris’s [11] on two-error diagnosis....................33


List of Figures

Figure 1: A circuit with a single error . The primary inputs are X1, X2, and X3. The primary outputs are F1 and F2. The internal wires (nodes) are A, B, C, and D. B1~B4 are branch wires. The gate marked as "wrong gate" is the error source...............................................6
Figure 2: Backward propagation rules......................11
Figure 3: Applying backward propagation rules to parallel bits......................................................12
Figure 4: A simple circuit with two error source..........18
Figure 5: A circuit with two error source.................19
Figure 6: The sensitization sets of every node in the circuit of Figure 5.......................................21
Figure 7: The flow chart of the overall approach..........25

                                

[1] M. Abramovici, P. R. Menon, and D. T. Miller, “Critical path tracing - an alternative to fault simulation,” in Proc. 20th Conf. on Design Automation, pp. 214-220, 1983.

[2] P.-Y. Chung, Y.-M. Wang, and I. N. Hajj, “Diagnosis and correction of logic design errors in digital circuits,” in Proc. Design Automation Conf., pp. 503-508, June. 1993.

[3] S.-Y. Huang, K.-T. Cheng, K.-C. Chen, and D.-I. Cheng “ErrorTracer: A fault simulation-based approach to design error diagnosis,” in Proc. Int. Test Conf., pp. 974-981, Feb. 1997.

[4] A. Kuehlmann, D.-I. Cheng, A. Srinivasan, and D. P. LaPotin, “Error diagnosis for transistor-level verification,” in Proc. Design Automation Conf., pp. 218-224, June. 1994.

[5] C.-C. Lin, K.-C. Chen, S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, “Logic synthesis for engineering change,” in Proc. Design Automation Conf., pp. 647-652, June. 1995.

[6] C.-C. Lin, K.-C. Chen, D.-I. Cheng, and M. Marek - Sadowska, “Logic rectification and synthesis for engineering change,” in Proc. Asian and South Pacific Design Automation Conf., pp. 301-309, 1995.

[7] I. Pomeranz and S. M. Reddy, “On correction of multiple design errors,”IEEE Trans. CAD., vol. 14, pp. 255-264, Feb. 1995.

[8] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni - Vincentelli, “SIS: A system for sequential circuit synthesis,” Technical Report UCB/ERL M92/41, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, May. 1992.

[9] M. Tomita, T. Yamamoto, F. Sumikawa, and K. Hirano “Rectification of Multiple Logic Design Errors in Multiple Output Circuits,” in Proc. Design Automation Conf., pp. 212-217, June. 1994.

[10] A. Veneris and I. N. Hajj, “A fast algorithm for locating and correcting simple design errors in VLSI digital circuits,” in Proc. Great Lake Symp. on VLSI Design, pp. 45-50, Mar. 1997.

[11] A. Veneris and I. N. Hajj, “Design error diagnosis and correction via test vector simulation,” IEEE Trans. CAD., vol. 18, no. 12, pp. 1803-1816, Dec. 1999.

[12] A. Veneris, J.-B. Liu, M. Amiri, and M. S. Abadir, “Incremental Diagnosis and Correction of Multiple Faults and Errors,” Proc. Design, Automation and Test in Europe Conference and Exhibition, pp. 716-721, 2002.

[13] J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McGarthy, “Fault simulation for structured VLSI,” in VLSI Syst. Design, pp. 20-32, Dec. 1985.

[14] S.-C. Wu and C.-Y. Wang, “PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking,” in VLSI-SoC, pp.104-109, Oct. 2006.

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