簡易檢索 / 詳目顯示

研究生: 劉佳雯
Jia-Wen Liu
論文名稱: 薄膜電晶體各種效應與照光操作之下的特性分析
Analysis of thin-film transistors with various nonidealities and light illumination
指導教授: 洪勝富
Sheng-Fu Horng
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2006
畢業學年度: 94
語文別: 中文
論文頁數: 66
中文關鍵詞: 薄膜電晶體亮度不均
外文關鍵詞: thin film transistor, MURA
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在論文第一部份的研究,是模擬在薄膜電晶體製程步驟中,有一些缺陷對電流-電壓曲線所造成的影響。所以就元件軟體內的材料設定作改變,模擬改變結構部份區域來探討影響的情況。
    論文第二部份,提出整合非揮發性記憶體結構(N通道)在每一個畫素中的想法,以通道二次電子注入機制與通道熱載子注入機制為基礎,我們期望非揮發性記憶體結構在有照光條件操作寫入下,會比未照光操作下注入更多的負電荷於浮動閘極內,因此會有較高的臨界電壓,導致發光二極體的亮度變暗。所以若將較亮的面板區域按此想法操作下,會使得亮度變暗,有利於達到亮度均勻和顏色均勻的情況。所以本論文則是建構非揮發記憶體結構,模擬在照光與未照光下的臨界電壓偏移情況,並改進結構使得在照光和未照光下臨界電壓偏移差值越多。
    由模擬數據看來,將基板改薄、濃度增加、照光在源極區域可以達到期望的特性。有結構於汲極電壓為12伏特、閘極電壓為8伏特、基板電壓為-8伏特,照光(照光強度為2.5瓦特每平方公分)操作下與未照光操作下臨界電壓偏移差約23.54%。


    The first part of the thesis is to investigate by simulation the I-V curve of the thin film transistor with various defects during manufacturing processes. We change material parameters to simulate the devices in MEDICI and study the effects of various defects in the device structures.
    In the second part of the thesis, we study the integration of a nonvolatile memory into the pixel circuit so that the threshold voltage increases more at high illumination. As the threshold voltage increases, the brightness of the pixel decreases, leading to better uniformity in brightness.
    We found that VD=12volt、VG=8volt、VB=-8volt,the shift in threshold voltage between dark and illumination can be as high as 23.54%.

    摘要 i ABSTRACT ii 致謝 iii 目錄 iv 圖目錄 vi 表目錄 viii 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 2 1.3 研究架構 3 第二章 文獻回顧與模擬軟體 4 2.0 前言 4 2.1 有機薄膜電晶體 4 2.2 通道二次電子注入機制(CHISEL) 8 2.3 模擬軟體簡介 14 第三章 薄膜電晶體的各種效應 21 3.0 前言 21 3.1修改材料參數的基本結構 21 3.2薄膜電晶體半導體材料濃度分佈對電流-電壓的影響 24 3.3薄膜電晶體不理想結構對電流-電壓的影響 28 3.4薄膜電晶體的介面不平坦情況 33 第四章 解決顯示器亮度不均的現象 35 4.0 前言 35 4.1 根據文獻內容的研究工作 35 4-2 著重在照光與未照光下的臨界電壓偏移差的比較 44 4-3 進一步改進結構研究 48 4-4 改變基板電極位置 53 4.5 放大通道長度與閘極氧化層厚度的研究 61 第五章 結論 64 參考文獻 65

    〔2-1-1〕Christos D. Dimitrakopoulous and Patrick R.L. Malenfant, “Organic Thin Film Transistors for large area electronics”, Adv. Mater. 2002,14,January 16
    〔2-1-2〕H. Sirringhaus, N. Tessler, Richard H. Friend, “Integrated Optoelectronic Devices Based on conjugated polymers”, Science 280,1741 (1998)
    〔2-2-1〕J. D. Bude, A. Frommer, M. R. Pinto, G. R. Weber, ” EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing”, in IEDM Tech, Dig., 1995, pp. 989-989
    〔2-2-2〕Souvik Mahapatra, S. Shukuri, and Jeff Bude, “CHISEL Flash EEPROM—Part I: Performance and scaling”, IEEE Trans. Electron Devices, vol. 49, pp. 1296-1301, 2002
    〔2-2-3〕J. D. Bude, “Gate current by impact ionization feedback in sub-micron MOSFET technologies,” in Symp. VLSI Technology Dig. Tech. Papers, 1995, pp. 101–102.
    〔2-2-4〕Marco Mastrapasqua and Jeff D. Bude, “Electron and hole impact ionization in deep sub-micron MOSFETs”, Microelectronic Engineering 28 (1995) 293-300.
    〔2-2-5〕B. Marchand, D. Blachier, C. Leronx, G. ghibaudo,F. Balestra and G. Reimbold, “Generation of hot carriers by secondary impact ionization in deep submicron devices : model and light emission characterization”, IEEE, 2000.
    〔2-3-1〕Avant! Corporation, “Medici Two-Dimensional Device Simulation Program User Manual”, TCAD Business Unit, December 2000.
    〔2-3-2〕D. J. Roulston, N. D. Arora and S. G. Chamberlain, “Modeling and Measurement of Minority-Carrier Lifetime Versus Doping in Diffused Layers of n+-p Silicon Diodes”, IEEE Trans. Electron Devices, Vol. ED-29, pp. 284-291, Feb. 1982.
    〔2-3-3〕D. M. Caughey and R. E. Thomas, “Carrier Mobilities in Silicon Empirically Related to Doping and Field”, Proc. IEEE, Vol. 55, pp. 2192-2193, 1967.
    〔2-3-4〕S. Selberherr, “Process and Device Modeling for VLSI”, Microelectron. Reliab., Vol. 24, No. 2, pp. 225-257, 1984.
    〔2-3-5〕K. Yamaguchi, “Field-Dependent Mobility Model for Two-Dimensional Numerical Analysis of MOSFET’s,” IEEE Trans. Electron Devices, Vol. ED-26, pp. 1068-1074, July 1979.
    〔2-3-6〕K. Yamaguchi, “A Mobility Model for Carriers in the MOS Inversion Layer,” IEEE Trans. Electron Devices, Vol. ED-30, pp. 658-663, June 1983.
    〔2-3-7〕D. M. Caughey and R. E. Thomas, “Carrier Mobilities in Silicon Empirically Related to Doping and Field,” Proc. IEEE, Vol. 55, pp. 2192-2193, 1967.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE