近年來，3D IC製程技術發展日趨成熟，用於解決傳統晶片效能和功率消耗的問題，由於導線層內的介質材料和晶片黏合材料使得3D IC散熱較傳統晶片來的不易。此外，晶圓薄化技術及熱堆疊效應使3D IC熱問題更為嚴重。高溫操作和高溫度梯度都將會使效能和晶片可靠度降低，因此在設計時就需考量3D IC內的熱效能。
佈局後實行熱點分析可在設計早期時快速檢查3D IC的熱分布來避免熱點相互作用和熱堆疊的情況發生。因此，我們結合了分析法和數值方法以及利用邏輯閘層級(gate-level)功率評估方式實行暫態和穩態熱點分析。此外，我們使用經驗公式來評估導線層的熱傳導係數，這將比使用平均熱傳導係數來得精準。
我們以3D-SIC的技術建立同質多核心微處理器架構並實行熱點分析。從模擬結果發現在3D IC內熱點不一定會發生在高功耗源的地方而是受到其他層的熱點影響，且晶圓薄化技術造成熱效能降低。導線層和黏合層內熱絕緣材料是造成3D IC散熱不易的主因，且厚度越高將使熱點面積和尖峰溫度提升，然而，TSV在黏合層可以明顯改善3D IC的熱效能。此外，我們發現未考慮導線和TSV的功耗在最上層晶片會有5.88K的峰值誤差，而使用平均熱傳導係數評估導線層會有最上層晶片1.8K的峰值誤差。

3D integrated circuits can eliminate the effect by using intra-layer interconnects. However, thermal issue in 3D ICs becomes much more severe than in 2D ICs because thinned silicon substrate of each stacked die reduces the heat spreading effect and makes power density to increase due to heat stacking effect. Besides, the bonding material and the back-end-of-line dielectric are heat barriers to heat conduction. High temperature and temperature gradient will deteriorate the reliability and reduce the performance. Therefore, the thermal performance in 3D ICs needs to be considered in early design time and thermal analysis plays an important rule in the 3D IC design.
Floorplan-level thermal analysis for 3D ICs can provide fast approximation for temperature distribution on each stacked die and provide indications for the thermal management to avoid inter-die hotspot interaction and heat stacking effect in early design time. In this work, we combined the analytical method and numerical method for floorplan-level thermal analysis and proposed a gate-level power evaluation method for both transient and steady-state thermal analysis. Furthermore, We used empirical function to evaluate the effective thermal conductivity of BEOL layers which is accurate than the average weighted thermal conductivity used in many researches.
We constructed a homogeneous multi-core architecture by using OpenRISC IP cores in 3D-SIC as our thermal model for both transient and steady-state thermal simulation by HotSpot5.0. From the simulation results, we found that the hotspots can occur at the locations without high power sources and are influenced by the hotspots in other tiers. Wafer thinning technology worsens thermal performance in 3D ICs. Furthermore, BEOL layers and bonding layers with low-thermal-conductivity materials are heat barriers to heat conduction and induce larger hotspot footprint and higher peak temperature if with larger thickness. However, bonding layer with TSV insertion can improve thermal performance dramatically. The underestimation of the peak temperature in the top die is 5.88K if without taking BEOL and TSV power into account. Besides, we compared the average weighted thermal conductivity of BEOL layers to our method and caused 1.8K underestimation of the peak temperature in the top die because BEOL layers dominate the vertical temperature gradient.

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