準迴旋式的低密度奇偶查核碼(QC-LDPC code)在新一代的無線通訊系統上被廣泛的使用且納入規格中。並且被證實具有逼近向農極限(Shannon limit)的優越錯誤更正能力。在現今科技的進步下，要實現低密度同位檢查碼解碼器不再是不可能的事，並且有越來越多相關的研究正在進行。現今，有許多通訊系統採用低密度同位檢查碼作為它們的通道編碼(channel coding)，如802.11n和802.16e。雖然低密度同位檢查碼擁有出色的解碼性能，實現它卻從來不是一件簡單的事。在實作上仍然有許多挑戰。繞線複雜度、晶片面積與功率消耗等都是必需列入考量的面向。
在文獻中有一種高收斂速度的解碼器架構被提出，由於使用較少的運算單元，使得需要較長的運算時間。我們利用管線法 (pipeline) 有效的增加解碼吞吐量(throughput)。我們提出一種新穎的事前機率(APP value)的存取系統，以解決管線解碼器記憶體存取危機。本篇論文使用0.18微米1P5M的製程實作IEEE 802.16e無線傳輸規格中碼率為1/2的低密度奇偶查核碼，在時脈200Mhz的狀況下, 可以達到105Mbps(未包含iopad的延遲)。核心部份的面積大小為2.38x2.38mm^2 。由於LDPC令人詬病的高繞線複雜度在本架構所採用的解碼架構下也獲得解決, 因此繞線僅占整體面積三成，且能支援各種碼長的解碼。本晶片設計採用ASIC流程，首先以RTL code撰寫，到合成，到layout，經過各種模擬，驗證結果，證實我們整個系統架構是完整無誤的。

In new generation wireless communication system, quasi-cyclic low-density parity-check code is popularly used in WiMAX and fit into Standard Performance Evaluation Corporation(SPEC) of 802.16e. They provide performance that comes quite close to the Shannon limit. With the advanced technology, implementing LDPC code decoder is not an impossible thing and there are more and more researches on LDPC codes. There are also many communication systems adopt LDPC codes as their channel coding, such as 802.11n and 802.16e. Although LDPC codes have excellent decoding performance, realizing it is never an easy job. There still exist many challenges when implementing LDPC code decoder. The high routing complexity, large chip area and high power consumption all need to take into concerns.

In our paper, we proposed a decoder architecture which is focused on fast convergence speed. Since the lower calculating unit is used, we need longer calculating time. We use pipeline method to improve throughput efficiently. a new method of memory access is proposed to avoid hazards in accessing values of a posteriori probability from memories. This paper use 0.18um^2 1p5m to implement 1/2 code rate LDPC of IEEE 802.16e. At 200 MHz, the throughput can achieve 105Mbps(not include io pad delay). The core area is 2.38x2.38mm^2. The routing-problem can be solved by the proposed architecture, so the proportion of routing is about 30% of total area, and can support multi code length decoding. The design of chip is used ASIC flow. First, we write RTL code. Then, we synthesize our code. After various simulating, we verify result. We prove our whole system architecture is correct.

[1] M.Karkooti, P. Radosavljevic and J.R. Cavllaro, ”Con?gurable, high throughput, irregular LDPC decoder architecture tradeo? analysis and implementation,” in Proc. IEEE 2006 Application-speci?c Systems, Ar?chitectures and Processors (ASAP’06).
[2] Yeong-Luh Ueng Chung-Jay Yang Zong-Cheng Wu and Chen-Eng Wu "VLSI Decoding Architecture with Improved Convergence Speed and Reduced Decoding Latency for irregular LDPC Codes inWiMAX" ISCAS2008.
[3] R. Gallager, ”Low-density parity-check Codes,” IRE Trans. Inf. Theory, vol. 7, pp. 21-28, Jan. 1962.
[4] D. Mackay, “Good error correcting codes based on very sparse matrices,” IEEE Trans. Inform. Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.
[5] T.J. Richardson, M.A. Shokrollahi, and R.L. Urbanke, “Design of capacity-approaching irregular low-density parity-check codes,” IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.
[6] T.J. Richardson and R.L. Urbanke, “The capacity of low-density parity-check codes under message passing decoding ,” IEEE Trans. Inform. The?ory, vol. 47, no. 2, pp. 599-618, Feb. 2001.
[7] S. Chung, G. Forney, T.J. Richardson and R.L. Urbanke, “On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit,” IEEE Commun. Lett., vol. 5, no. 2, pp. 58-60, Feb. 2001.
[8] IEEE 802.11 Wireless LANs WWiSE Proposal: High Throughput exten?sion to the 802.11 Standard. IEEE 11-04-0886-00-000n
[9] Part 16: Air interface for ?xed and mobile broadband wireless access sys?tems amendment for physical and medium access control layers for com?bined ?xed and mobile operation in licensed bands, IEEE P802.16e-2005, 2005.
[10] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inform. Theory, vol. IT-27, pp. 533-547, Sep. 1981.
[11] M. Fossorier, M. Mihaljevic, and H. Imai, ”Reduced complexity iterative decoding of low-density parity check codes based on belief propagation”, IEEE Trans. Commum., vol. 47, pp. 673-680, May 1999.
[12] L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Inform. Theory, IT-20, pp. 284-287, March 1974.
[13] J. Chen and M. Fossorier, ”Density evolution for two improved BP-based decoding algorithms of LDPC codes,” IEEE Commum. Lett., vol. 6, pp. 208-210, May 2002.
[14] A. Blanksby and C. Howland, ”A 690-mW 1-Gb/s, rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar. 2002.
[15] E. Yeo, P. Pakzad, B. Nikoli′c, and V. Anantharam, ” VLSI architec?tures for iterative deocders in magnetic recording channels ,” IEEE Trans. Magn., vol. 37, pp. 748-755, Mar. 2001.
[16] S. Lin and D. J. Costello, Jr., Error Control Coding. Pearson Prentice-Hall, 2nd ed. 2004
[17] Y. Chen and K. K. Parhi, ”Overlapped message passing for quasi-cyclic low-density parity check codes,” IEEE Trans. Circuits Syst. I, Reg. Pa?pers, vol. 51, no. 6, pp. 1106-1113, Jun. 2004.
[18] S. H. Kang and I. C. Park, ”Loosely coupled memory-based decoding architecture for low density parity check codes,” IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 53, no. 5, pp. 1045-1056, May 2006.
[19] H.Behairy and S.-C. Chang, ”Parallel concatenated Gallager codes,” Elec?tronics Letters, vol.36, no.24, pp. 2025-2026, Nov. 2000.
[20] O. Pothier, L. Brunel and J. Boutros, ”A low complexity FEC scheme based on the intersection of interleaved clock codes,” in Proc. IEEE 49 st Semiannual Vehicular Technology Conference, vol. 1, pp. 274-278, 16-20 May, 1999.
[21] H. Sankar and K.R. Narayanan, ”Memory-e?cient sum-product decoding of LDPC codes,” IEEE Trans. on Communications, vol.52, no. 8, pp. 1225-1230, August 2004.
[22] D.E Hocevar, ”A reduced complexity decoder architecture via layered decoding of LDPC codes,” IEEE Workshop on Signal Processing Systems, 2004 (SIPS ’04) pp. 107-112, 13-15 Oct. 2004.
[23] D.E Hovevar, ”LDPC code construction with ?exible hardware implemen?tation”, in Proc. IEEE Int. Conf. Commu, Anchorage, AK, pp. 2708-2712, 11-15 May 2003.
[24] M. M. Mansour and N. R. Shanbhag, ”High-throughput LDPC decoders,” IEEE Trans. VLSI System, vol. 11, no. 6, pp. 976-996, Dec. 2003.
[25] H. Zhong; T. Zhang; ”Block-LDPC: A practical LDPC coding system design approach,” IEEE Transactions on Circuit and Systems–I: regular papers, Vol. 52, No. 4, pp.766-775 , April 2005
[26] K. K. Gunnam, G. S. Choi, M. B. Yeary, and M. Atiquzzaman, ”VLSI architectures for layered decoding for irregular LDPC codes of WiMAX,” in Proc. IEEE Int. Conf. Commu, 2007, pp. 4542-4547.
[27] Y.-L Ueng and C.-C. Cheng, ”A fast-convergence decoding method and memory-e?cient VLSI decoder architecture for irregular LDPC codes used in the IEEE 802.16e standard,” in Proc. IEEE 66 st Semiannual Vehicular Technology Conference, Baltimore, USA, Sept. 30-Oct. 3, 2007.
[28] Y.-L. Ueng, C.-J. Yang, Z.-C. Wu, C.-E. Wu, and Y.-L. Wang, ”VLSI decoding architecture with improved convergence speed and reduced de?coding latency for irregular LDPC codes in WiMAX,” in Proc. IEEE International Symposium on Circuits and Systems, Seattle, USA, 18-21, May, 2008 (Accepted).
[29] M. Karkooti, P. Radosavljevic and J.R. Cavllaro, ”Con?gurable, high throughput, irregular LDPC decoder architecture tradeo? analysis and implementation,” in Proc. IEEE 2006 Application-speci?c Systems, Ar?chitectures and Processors (ASAP’06).
[30] C.P. Fewer, M.F. Flanagan, and A. D. Fagan, ”A versatile variable rate LDPC codec architecture,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 10, pp. 2240-2250, Oct. 2007.
[31] S. Lin and D. J. Costello, Jr.,“Error Control Coding”,Pearson Prentice-Hall, 2nd,2004
[32] (Online) http://www.ieee802.org/16/tge/
[33] RuiyuanHu, JingLi, and KurtasE.,“Quantization and quantization sen?sitivity of soft-output product codes for fast-speed applications, ”2004 IEEE/Sarno? Symposium onAdvances in Wired and Wireless Communi?cation, 26-27 Apr 2004, pp. 175-178
[34] T. Brack, M. Alles, F. Kienle, and N. Wehn, ”A synthesizable IP core for WiMAX 802.16e LDPC code decoding,” in Proc. IEEE Annual Interna?tional Symposium on Personal Indoor and Mobile Radio Communications (PIMRC 2006), Helsinki, Finland, 11-14 September, 2006.
[35] X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A.-Y. Wu, ”An 8.29mm2 52-mW multi-mode LDPC decoder design for Mobile WiMAX system in 0.131m CMOS process” IEEE J. Solid-State Circuits, vol.43, pp. 672-683, March 2008.
[36] C.-H. Liu, S.-W. Yen, C.-L. Chen, H.-C. Chang, C.Y. Lee, Y.-S. Hsu, and S.-J. Jou, ”An LDPC decoder chip based on self-routing network for IEEE 802.16e Applications,” IEEE J. Solid-State Circuits, vol.43, pp. 684-694, March 2008.
[37] Z. -C. Wu,“An LDPC decoder with low area complexity for mobile WiMAX”M.S Thesis, National Tsing Hua University, Hsinchu, Taiwan, R.O.C., August 2008.