隨著顯示技術的進步，新一代的顯示裝置相較於傳統顯示裝置而言，已能夠有效改善亮度的動態顯示範圍。利用逆色調映射 (Inverse Tone Mapping) 的方法，可將低動態亮度範圍的影像，轉換至高動態亮度範圍 (High Dynamic Range , HDR)。這方法當中，一些方法需要利用相同場景的不同曝光影像，才能將低動態亮度範圍的影像轉換至 高動態亮度範圍，然而對於大多數影像或是視訊而言，只能取得單一曝光的影像或視訊。因此在本篇論文中，我們提出虛擬多重曝光影像以及區域對比增強的方法，產生高動態亮度範圍的影像。首先，我們提出利用能夠改變不同曝光值的S-曲線，將一張低動態亮度範圍的影像，產生多張虛擬曝光的影像。由於在虛擬曝光影像中的某些區域包含了一些，能夠被觀察的影像細節，因此我們利用區域對比增強的方法，針對在不同曝光影像中的的某些區域增強其對比，進而利用色調合成的方法產生高動態亮度範圍的影像。在我們的方法中，我們針對兩種類型的區域做區域對比增強，分別為最暗影像的最亮區域，以及最亮影像的最暗區域。在區域對比增強後所得到的高動態亮度範圍的影像，和其他逆色調映射的方法做比較，可以發現我們的方法在錯誤對比的量測中，對比的錯誤總數是比較低的。

此外，在這篇論文中，我們將我們的方法在不同的多處理器的環境中，分析其運算效能並加以實現。經由分析之後發現，我們的演算法當中，產生五張不同曝光的影像，以及計算不同的權重值有最高的運算量，因此我們將這兩部分的運算放在不同處理器中平行處理。經由實驗發現，我們將產生五張不同曝光的影像，以及計算不同的權重值平行化處理之後，指令數目有效的降低，在六個處理器平行處理的環境中，運算時間可減少大約70%。經由實驗證實，我們所提出的方法，很容易在多處理器的平台上實現，並能有效提高運算效能。

為了能將高動態亮度範圍的影像或視訊，顯示在傳統低動態亮度範圍的液晶顯示裝置上，所採用的方法一般稱為色調映射。過去數十年期間，許多色調映射 (Tone Mapping)的方法，陸續被提出。一個理想的色調映射處理器，應該要包含一顆功能較為強健的處理器，同時應具備面積小，及低功耗的特性，以提高處理色調映射的彈性。因此我們選擇安謀 ARM 處理器為主的系統晶片平台，同時在此系統晶片平台上，開發色調映射應用的特殊應用積體電路晶片。在本篇論文中，我們經由系統最佳化的分析，開發具有硬體與軟體最佳化的色調映射系統晶片。我們整合了全影像色調映射與以局部影像為處理單元的區域影像色調映射，同時我們經由系統分析，開發最佳的軟硬體架構。在我們的最佳化的開發過程中，有四個主要的步驟分別是 :定義功能性模組，運算功能的強化，硬體與軟體功能模組的區分，以及成本函數的分析。根據我們所提出的架構，我們成功的開發了一個具有整合全影像色調映射與區域影像色調映射的色調映射系統晶片，針對不同的應用可以選擇合適的色調映射的方法。我們所開發的系統晶片使用台積電0.13微米的製程，時脈頻率可達100MHz，面積為8.1mm^2，可處理影像大小為 1024X768，且每秒可處理60張影像。經由軟硬體最佳化後，硬體面積可以有效降低達50%。

New generations of display technologies provide a significantly improved dynamic range compared to conventional display devices. Inverse tone mapping methods have been proposed to convert low dynamic range (LDR) images to high dynamic range (HDR) ones, and several of them require multiple-exposures LDR images of the same scene as inputs. However, the vast majority of LDR images and videos available have only one single exposure. In this dissertation, we propose a region-based enhancement of the pseudo exposures to generate an HDR image. First, we present an exposure dependent $S$ curve to convert one
LDR image to the pseudo-multiple-exposures images.
Only certain regions of the pseudo-multiple-exposures images contain noticeable detailed information. We propose a region-based enhancement on the pseudo-multiple-exposures images to boost details in the most distinct region. Thereby the region-enhanced pseudo-multiple-exposures images are fused into an HDR image. The fused image thus enhances details in the brightest region of the darkest image and the darkest region of the brightest image. Compared with other inverse tone mapped methods, our method generates the lower total contrast error which is measured under the dynamic range independent image quality assessment method.

In this dissertation, we analyze the performance of implementing inverse tone mapping operation in various multi-core environments. We parallelize the two procedures to produce five HDR images and different weighting values. The ratio of the instruction counts for producing five HDR images and weighting values are both reduced, and the total simulation time decreases around 70% under six-core environment. The reduction is because these functions are implemented parallel with multi-thread on a multi-core platform. The analysis of hardware performance shows that our proposed method is easy to be realized in a multi-core system to speed up the performance.

The technology to display HDR images or videos on conventional LCD devices is called tone mapping which has the different algorithms that have been developed in the past decade. An ideal HDR tone mapping processor should have some characteristics such as a robust core functionality, high flexibility, and low power consumption. Therefore, an $ARM^{TM}$-core-based System-on-Chip (SoC) platform with an HDR tone mapping application-specific integrated circuit (ASIC) is suitable for such applications. In this dissertation, we present a systematic methodology for the development of a tone mapping processor of optimized architecture using an ARM SoC platform, and illustrate the use of this novel HDR tone mapping processor for both photographic and gradient compression. Optimization is achieved through four major steps: common module extraction, computation of power enhancement, hardware/software partition, and cost function analysis. Based on our proposed scheme, we present an integrated photographic and gradient tone-mapping processor that can be configured for various applications. This newly-developed processor can process the image size 1024X768 at 60 frame per second, runs at 100 MHz and consumes a core area of 8.1 mm^2 under TSMC 0.13 um technology, resulting in a 50% improvement in speed and area as compared with previously described processors.

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