寬能帶半導體材料（Wide band gap semiconductor material）在最近幾十年的研究中，有許多不錯的研究結果發表，為下一個世代半導體元件材料的發展主流。碳化矽(Silicon Carbon)是寬能帶半導體材料之一，相較於其他的半導體材料如矽、鍺、砷化鎵而言，寬能帶半導體材料碳化矽(SiC)的電子元件有許多優勢，適合運用於高功率元件。
本篇論文主旨在進行4H-SiC橫向高電壓的接面場效電晶體的研製。元件設計利用雙漂移區域的結構以降低表面電場並用場平板保護閘極及汲極，以提高崩潰電壓。此外我們也結合絕緣基板，目的為避免基板助長空乏效應。本論文利用蝕刻的方式形成雙漂移區域降低表面電場的結構，可以減少離子摻雜的製程步驟。
在本論文中，我們將製作不同長度的漂移區、不同的雙漂移區域降低表面電場結構長度、與不同長度的場平板結構。從量測結果可看出，當漂移區長度越長，則元件的崩潰電壓越高。經過量測後，雙漂移區的接面場效電晶體在閘極寬度為200µm及漂移區為100µm時，可獲得導通電阻454 mΩ-cm2 ，崩潰電壓可達4199伏特。

The main purpose of this thesis is to fabricate a high voltage 4H-SiC lateral junction field effect transistor. In order to reduce the specific-on-resistance and enhance the breakdown voltage, we use a two-zone design in the drift region, and field plates at the gate and the drain. Furthermore, we also use the semi-insulating substrate to reduce the substrate-assisted-depletion effect. By using the reactive ion etch to fabricate the two-zone structure, we can avoid the difficult implantation process in SiC.
The measurement results show that the breakdown voltage increases with the drift region length. A two-zone SiC JFET with gate width of 200µm and a lateral drift-region length of 100µm can achieve breakdown voltage is 4199V. The specific-on-resistance of this device is 454 mΩ-cm2 .

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