由於覆晶結構具輕、薄與小尺寸等特質，且因其良好的散熱及高密度特性相當符合下一代封裝結構之趨勢，因此近年來已引起廣泛研究。因覆晶封裝結構中的矽晶片與有機基板間的熱膨脹係數差異頗大，故需填充底膠以確保其長時可靠性。然因底膠通常為熱固性的高分子聚合物，不僅固化過程過於耗時，同時經過烘烤固化後若發現晶片功能出現瑕疵，將無法進行重工。
為避免覆晶封裝結構中使用底膠填充之限制，且同時保有良好的可靠性，本文提出無底膠附加限制層覆晶封裝結構的新概念。此新型覆晶結構在基板底部貼附一層熱膨脹係數與矽晶片相似之限制層，使整體熱膨脹係數之差異減小以保持可接受的可靠度。本研究針對無底膠覆晶封裝結構建立二維有限元模型，對各個參數進行參數化分析。並進一步建構三維有限元模型探討限制層經切割或開孔與否對無底膠附加限制層覆晶封裝之可靠度影響。

由於探討限制層開孔或切割需建構三維有限元模型，分析時因計算量過於龐大，故本研究導入等效樑原理，使用與實體錫球力學行為相近之等效樑取代實體錫球，大幅降低計算量並得到合理的結果。本文所使用之等效樑概念對日後從事相關研究之人員提供另一種預測封裝熱應力/應變的方法。

Abstract
Flip chip has distinguishing characteristics of light weight, thin, and small dimensions. This type of package has brought about broad study of electronic industrial because of its good thermal property and high I/O density. CTE mismatch between silicon and BT board is so colossal that flip chip need filling underfill to keep the long-term reliability. Moreover, underfill is usually thermosetting polymer and the process of hardening is time-consuming. If the die is found it cannot work after baking of underfill, the die cannot be replaced.

For avoiding the disadvantage of filling the underfill and keeping good reliability, this research proposes a novel concept of no underfill with constraint layer flip chip package. This novel flip chip package is bonded a constraint layer with similar CTE of die on the bottom of BT board, and furthermore the CTE mismatch can be diminished and the package can obtain available reliability. In this research, the 2D model will be constructed to do parametric studies. Moreover, whether the cutting and opening hole of constraint layer can enhance the reliability will be discussed.

When discussing the cutting and opening hole of constraint layer, the 3D finite element model is necessary. Due to the calculation is so huge, the equivalent beam theory is applied in this study. The 3D ball of this study will be replaced by equivalent beam that possesses similar force-displacement relationship of 3D ball and the CUP time will be decreased and simultaneously we can obtain reasonable solution. This paper provides another methodology for analyzing thermal stress/strain of electronic package.

【1】劉振南, ”無底膠新型覆晶封裝結構之設計與可靠度分析” ,國立清華大學碩士論文,June 2000.
【2】 R. Darveaux, K. Barnerji, A. Mawer, and G. Dody, “Reliability of Plastic Ball Grid Array Assembly,” Ball Grid ArraybTechnology, J. Lau, ed., McGraw-Hill, Inc., New York,1995, pp. 379-442.
【3】 K.N. Chiang, W. L. Chen, ”Electronic Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array”, ASME Transaction Journal of Electronic Packaging. Vol. 120, June 1998. pp. 175-178
【4】 H. C. Cheng, K. N. Chiang, C. K. Chen, “Parametric Analysis of Thermally Enhanced BGA Reliability Using A Finite-Volume-Weighted Averaging Technique”, International Mechanical Engineering Congress and Exposition, The Winter Annual Meeting of ASME, conf. 1998.pp.1-9
【5】 Z. Qian and S. Liu, “On the Life Prediction and Accelerated Testing of Solder Joints”, EEP-Vol. 24, Thermo-Mechanical Characterization of Evolving Packaging Materials and Structures, ASME, 1998.pp.132-140
【6】 J. P. Clech, “BGA, Flip-Chip and CSP Solder Joint Reliability: of the Importance of Model Validation”, InterPack, 1999.pp.112-121
【7】 V. Sarihan, “Energy Based Methodology for Damage and Life Prediction of Solder Joints under Thermal Cycling”, Electronic Components and Technology Conference, Proceedings, 43rd, IEEE, 1993, pp 32-38
【8】 Cho-Pin Yeh, 1996, “Parametric Finite Element Analysis of Flip Chip Reliability”. The International Journal of Microcircuits and Electronic Packaging. Vol. 19. Number 2, Second Quarter.pp.120-127.
【9】 L. L. Mercado and V. Sarihan, “Predictive Design of Flip-Chip PBGA for High Reliability and Low Cost”, Electronic Components and Technology Conference, 1999.pp.72-80
【10】 J. Sommer, R. Dudek, E. Kaulfersch, A. Schubert, and B. Michel, ”Thermo-Mechanical FE Analysis and Micro Deformation Measurements-Basis for Reliability Assessment of Microelectronic Components”, InterSociety Conference on Thermal Phenomena, IEEE, 1998.pp.25-31
【11】 Ali O. Ayhan and Herman F. Nied, “Finite Element Analysis of Interface Cracking in Semiconductor Packages”,Transactions on Components and Packaging Technology ,IEEE ,December 1999.pp.503-511
【12】 A. R. Syed, “Creep Crack Growth Prediction of Solder Joints During Temperature Cycling-An Engineering Approach” ,Transactions of ASME. Vol. 117, June 1995, pp.116-121.
【13】 J. Sommer, R. Dudek, E. Kaulfersch, A. Schubert, and B. Michel, ”Thermo-Mechanical FE Analysis and Micro Deformation Measurements-Basis for Reliability Assessment of Microelectronic Components”, InterSociety Conference on Thermal Phenomena, IEEE, 1998.pp.17-28
【14】 Z. Johnson, ”Implementation of and Extensions to Darveaux’s Approach to Finite-Element Simulation of BGA Solder Joint Reliability”, Electronic Components and Technology Conference, IEEE, 1999.pp.56-67
【15】M. Ikemizu, Y. Fukuzawa, “CSP Solder Reliability”, IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium, 1997.pp.447-451
【16】 K. N. Chiang, H. C. Cheng, and W. H. Chen, “Large-Scaled 3-D Area Array Electronic Packaging Analysis”, Journal of Electronic Packaging,1999.pp.1-10
【17】 K. N. Chiang, “A Large Scale Finite Element Analysis for Ball Grid Array Package Design”, Invited paper, HPC’98 Conference, Singapore, Sept.22-25, 1998
【18】 H. C. Cheng, K. N. Chiang, and M. H. Lee, “An Effect Approach for Three-Dimensional Finite Element Analysis of Ball Grid Array Typed Packages”, Journal of Electronic Packaging, Vol.120, June 1998, pp.129-134
【19】 C. A. Yuan and K. N. Chiang, “Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packging”, Euro Sim E Thermal & Mechanical, Simulation in (Micro) Electronics, 2001, pp.154-159
【20】 H. D. Solomon, “Fatigue of 60/40 Solder”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-9, 1986, pp. 91-104
【21】 C. A. Yuan