隨著現今半導體製程不斷的快速進步，元件中的最小線寬亦愈趨縮減，使得製程中所產生的製程變異影響更鉅。在積體電路量產之前，評估電路本身的效能是非常重要的，而在現今的半導體製程中，光學微影是其中最關鍵的製程步驟。因此，透過光學微影模擬工具，我們可以很迅速的檢查出製程變動對於電路的影響，進而估測電路的效能，並且在製造電路之前改善其設計。空間影像(aerial image)模擬是微影模擬最主要的步驟，影響關鍵尺寸(Critical Dimension, CD)的重要部份。在這篇論文中，我們探討了數種不同的空間影像模型，並且把焦點放在透鏡像差(lens aberration)對關鍵尺寸所產生的影響。我們的模型是以Hopkins理論 [1] 為基礎，對於部分同調性光源(partially coherent illumination)，利用透射相交係數(Transmission Cross-Coefficient, TCC)模擬整個曝光系統。我們把空間影像模擬產生出來的結果，跟U.C. Berkeley大學所提供的SPLAT軟體做比較，並且得到非常吻合的結果。接著在模擬製程中顯影(development)及蝕刻(etching)的步驟，我們利用了門檻模型以便於迅速得到關鍵尺寸。為了提升模擬器的效率，在模擬過程中，我們避免了對光學強度過低的區域作計算，對於空間密度較低的光罩圖形(layout pattern)，可大大的減少模擬時間。最後，我們應用我們的模擬器，在實際電路中之數種不同的基本組成單元(cell)，並且驗證我們的方法可以得到效能上的提升。

As the feature sizes in today’s semiconductor process become smaller, process variations have
great influences on the performance of integrated circuit (IC). Evaluating IC’s performance before
mass production is quite important and optical lithography is the key step in modern semiconductor
process. As a result, by optical lithography simulation, we can quickly examine the performance
of the ICs affected by process variations and furthermore modify the design before fabrication.
Aerial image simulation is the critical step in lithography simulation when determining the critical
dimension (CD). We investigate various simulation models of aerial image and focus on the
phenomenon of lens aberrations. Our model is based on Hopkins theory [1] which describes exposure
system via transmission cross-coefficient (TCC) for partially coherent systems. We show
the simulated aerial images agree well with the results from the simulator SPLAT [2]. A threshold
resist model is then applied to determine the CDs. To improve the performance, our simulator is
implemented to avoid calculations on low-intensity regions. Finally, several cell-level layouts are
used for demonstrating out simulator.

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