能帶工程介電層、複晶奈米線通道與無接面設計應用在三維電荷儲存式快閃記憶體之特性研究

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研究生：	諶俊元 Chen, Chun-Yuan
論文名稱：	能帶工程介電層、複晶奈米線通道與無接面設計應用在三維電荷儲存式快閃記憶體之特性研究 Effects of Bandgap-engineered Dielectrics, Polycrystalline Nanowire Channel and Junctionless Configuration on 3D Charge-trapping Flash Memory Devices
指導教授：	張廖貴術 Chang-Liao, Kuei-Shu
口試委員:	張廖貴術 Kuei-Shu Chang-Liao 趙天生 Tien-Sheng Chao 劉致為 Chee-Wee Liu 謝嘉民 Jia-Min Shieh 吳永俊 Yung-Chun Wu
學位類別：	博士 Doctor
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2014
畢業學年度：	103
語文別：	英文
論文頁數：	126
中文關鍵詞：	快閃記憶體、能帶工程、複晶奈米線通道、無接面設計
外文關鍵詞：	flash memory device, bandgap engineering, polycrystalline nanowire channel, junctionless transistor
相關次數：	點閱：2 下載：0
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複晶(polycrystalline)快閃記憶體近來被研究應用在三維(three-dimensional, 3D)NAND記憶體堆疊上。為了改善其電性與微縮，各種方式如非晶矽結晶、奈米線(nanowire, NW)通道結構以及能帶工程(bandgap engineering, BE)等皆被提出。在本論文中，我們首先探討由(低溫)富氮性(N-rich)氮化矽/二氧化矽所構成的堆疊式穿隧層對快閃記憶體電容造成的效應，應用此能帶工程穿隧層的元件，其寫入與抹除速度皆較單層穿隧層元件要高，但電荷保存力會稍微的下降。接著，我們研究氧化鉿/氮化矽堆疊形成的能帶工程式電荷儲存在複晶矽(polycrystalline silicon, poly-Si)快閃記憶體上的效應，發現此能帶工程式電荷儲存層在奈米線通道元件上能顯著提升記憶體元件的寫入抹除速度與電荷保持力。在第三個研究中我們將氧化鉿/氮化矽堆疊式電荷儲存層同時應用到無接面式(junctionless, JL)元件與反轉式(inversion mode, IM)快閃記憶體元件上，無接面元件不僅是寫入速度、電荷保持力與元件耐寫抹特性都比反轉式元件好，抹除速度也因氧化鉿/氮化矽儲存層的應用而改善到可與反轉式元件的相比擬。
除了能帶工程與無接面設計在複晶矽記憶體元件上的應用之外，我們也研究了矽鍺掩埋式通道(SiGe buried channel)在複晶矽上的應用，在複晶矽奈米線上磊晶矽鍺掩埋式通道有效提升了元件的寫入抹除速度與元件耐寫抹特性同時不減損電荷保持的能力。我們更提出了將複晶鍺(polycrystalline germanium, poly-Ge)奈米線應用於快閃記憶體元件上，複晶鍺因為自然摻雜的特性讓它在低溫又簡單的製程下就能完成無接面元件的製作，這樣的製程條件使複晶鍺無接面元件很適合用在三維記憶體微縮，電性的表現上也與一般所提出的複晶矽元件相近。
在最後一個研究中，我們實現一個可堆疊式的垂直閘極快閃記憶體，我們發現上下兩個元件有相近的寫入抹除速度以及可靠度的表現，在絕緣氧化層厚度為50奈米時，元件之間的寫入干擾很小，干擾免疫的記憶窗變化不大，因此這個結構很適合用來與能帶工程和不同通道材料整合應用。

Polycrystalline channel flash memory device has been studied for the application of three-dimensional (3D) NAND integration. For better device characteristics and continuous scaling, any methods have been proposed such as α-Si crystallization, nanowire (NW) channel and bandgap-engineered (BE) dielectrics. In this dissertation, effects of BE tunneling layer composed of nitrogen-rich (N-rich) SiN/SiO2 and low temperature (LT) N-rich SiN/ SiO2 stack are investigated on bulk capacitor device first. Devices with BE tunneling layer show faster programming and erasing (P/E) speeds but a little degraded retention performance. In the next study, a BE trapping layer composed of HfO2/SiN (HN) stack is applied to polycrystalline silicon (poly-Si) devices with planar and NW channel. Compared with the SiN trapping layer device, P/E speeds are improved by HN stacked trapping layer and the improvement is more effective on NW channel device. The retention performance of devices is also improved because of the lower conduction band level of HfO2. In the third study, HN stacked trapping layer is applied on both inversion-mode (IM) and junctionless-mode (JL) poly-Si flash device. With HN stacked trapping layer, JL device performs faster programming speed and comparable erasing speed with that of IM one, which is rarely seen in reported works which apply SiN as trapping layer and present slower erasing speed of JL device. Retention and endurance performances of JL device are also better than those of IM one.
Apart from the applications of BE and JL configuration on poly-Si flash device, characteristics of poly-Si device with SiGe buried channel are also studied. P/E speeds and endurance performance are improved by SiGe buried channel without degrading the retention performance. In the next study, pure polycrystalline germanium (poly-Ge) JL flash memory device is proposed for lower fabrication temperature and complexity. The JL configuration is formed by the naturally p-type doping of poly-Ge film such that no additional implantation and activation are needed. Good operation characteristics are also observed. In the final study, a stackable vertical gate structure is demonstrated for 3D memory integration. It is found that the P/E speeds and reliability performances of top and bottom devices are similar. Small program disturb and large disturb-free window are observed with the 50-nm thick SiN isolation layer. The 3D stackable structure is also compatible for the integration with BE and different polycrystalline channel.

摘要    i
Abstract    iii
Contents    v
Table Captions    ix
Figure Captions    x
Chapter 1    Introduction    1
1    Crystallization for amorphous Si    1
1.1    Excimer laser crystallization    1
1.2    Metal-induced crystallization    2
1.3    Solid-phase crystallization    2
2    Nanowire channel and multiple gate structure    3
2.1    Nanowire channel    3
2.2    Multiple gate structure    3
3    High-κ dielectric and bandgap engineering    4
3.1    Charge-trapping type flash memory device    4
3.2    High-κ dielectrics    5
3.3    Bandgap engineering    6
4    Junctionless flash memory device    8
5    Three-dimensional (3D) stackable NAND flash memory    10
6    SiGe buried channel for flash memory application    11
7    Characteristics of Germanium film    12
7.1    Dopant behaviors in Ge film    13
7.2    Annealing strategies of dopants in Ge film    14
8    Research motivation    16
9    Outline of dissertation    17
Chapter 2    Basic Operations of Flash Memory Device    31
1    Carrier transportation    31
1.1    Flower-Nordheim (FN) tunneling    32
1.2    Direct band-to-band tunneling (DT)    33
1.3    Modified Flower-Nordheim (MFN) tunneling    33
2    Retention property    34
3    Endurance property    35
4    Gate and drain disturb    36
Chapter 3    Improved Programming/Erasing Speed of Charge-trapping Flash Device with Tunneling Layer Formed by Low Temperature Nitrogen-Rich SiN/SiO2 Stack    40
1    Introduction    40
2    Device fabrication    42
3    Results and discussion    43
4    Conclusions    47
Chapter 4    Improved Programming and Erasing Speeds of Poly-Si Flash Memory Device by HfO2/SiN Bandgap-Engineered Trapping Layer    58
1    Introduction    58
2    Device fabrication    60
3    Results and discussion    62
4    Conclusions    63
Chapter 5    Improved Erasing Speed in Junctionless Flash Memory Device by HfO2/SiN Stacked Trapping Layer    69
1    Introduction    69
2    Device fabrication    70
3    Results and discussion    71
4    Conclusions    73
Chapter 6    Enhanced Operation Characteristics in Poly-Si Nanowire Charge-Trapping Flash Memory Device With SiGe Buried Channel    78
1    Introduction    78
2    Device fabrication    79
3    Results and discussion    81
4    Conclusions    83
Chapter 7    Poly-Ge Junctionless Flash Memory Device With Nanowire Channel    87
1    Introduction    87
2    Device fabrication    88
3    Results and discussion    90
4    Conclusions    92
Chapter 8    Vertically Stacked Junctionless Charge-Trapping Flash Memory Devices by Adopting In Situ Doped Poly-silicon Channel    98
1    Introduction    98
2    Device fabrication    99
3    Results and discussion    101
4    Conclusions    102
Chapter 9    Conclusions and Suggestions    109
1    Conclusions    109
2    Suggestions for future work    110
2.1    Suggestions for bandgap-engineered (BE) dielectrics    111
2.2    Suggestions for junctionless (JL) flash memory device    111
2.3    Suggestions for SiGe buried channel and poly-Ge flash device    111
2.4    Suggestions for 3D stackable flash memory structure    112
References    113
Publication list    123
Published papers    123
Conference papers    124

                                

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