隨著先進製程的發展，金屬的線寬愈來愈小、電阻愈來愈大。金屬線對時序以及電遷移的影響愈來愈明顯。為了解決這些問題，通孔柱技術被提出。然而，通孔柱會增加額外的繞線負擔。與此同時，先進製程中的設計規則愈來愈複雜、繞線資源也愈來愈少。在這些因素之下，細部繞線變得比以往更加困難。而引腳可連接性更是其中最關鍵的議題之一。因此，在實體設計流程中加入對通孔柱插入和引腳可連接性的考量是必要的。然而，據我們所知，先前沒有任何研究同時針對這兩個議題做考量。本論文提出一個能在細部擺置階段同時考慮通孔柱插入以及引腳可連接性的演算法。我們的方法由一個有向無環圖的最短路徑演算法，以及一個重新決定單元順序的機制組成。我們首先將單列中固定順序的細部擺置優化問題轉為一個有向無環圖的最短路徑問題。並在解此問題的過程加入對於安插通孔柱和引腳可連接性的考量。在有必要時，則會使用重新排序的機制來改變目前的解，以協助我們在下一次的迭代中找到合法解。實驗結果顯示，和原先的擺置結果相比，違反設計規則的數量減少97.08%、細部繞線的時間減少25.1%，且難以連接的引腳數量也減少了87.22%，而僅增加0.33%線長的成本。

With the scaling of technology nodes and the shrinking of feature size, the effects of circuit delay and electronic migration (EM) incurred from metal wires are tremendously increasing. A novel technique called via pillar is proposed to alleviate the EM impact and improve timing performance. However, via pillar increases the difficulty of routing as it occupies additional routing resources. Meanwhile, the complex design rules and limited routing resources make the detailed routing (DR) problem ever more difficult. Pin accessibility is one of the most crucial issues in advanced technology nodes. Thus, the consideration of via pillar insertion and pin accessibility in the physical design flow is necessary, especially in modern design. However, to our best knowledge, no previous research aims at co-optimizing these two issues. In this thesis, we propose a detailed placement refinement framework considering via pillar insertion and pin accessibility simultaneously. Our methodology is composed of a DAG-shortest-path algorithm and a re-ordering mechanism. We formulate a single-row fixed-order placement refinement problem as a DAG-shortest-path problem. Then, we assign via pillar cells to eligible positions as many as possible while optimizing the pin accessibility by the shortest-path algorithm. We also utilize the re-ordering mechanism to perturb the solution space of the DAG-shortest-path problem for further refining the placement if necessary. Experimental results show that our methodology helps reduce the number of DRC violations, detailed routing time, and hard-to-access pins significantly by 97.08%, 25.1%, and 87.22%, respectively, while only 0.33% overhead in wirelength.

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