本研究提出一種應用於CMOS影像感測器後端的高精度、低功耗ADC架構，旨在突破傳統單斜率（Single Slope）ADC在解析度與速度上的限制，滿足高解析度影像感測的需求。針對精準度和功耗的雙重要求，本設計採用基於Vcm的轉換方式，並加入誤差調變技術以有效抑制製程中電容陣列不匹配（Mismatch）帶來的誤差。此外，為解決此架構易受回踢雜訊影響的問題，本研究引入了低回踢雜訊比較器，確保系統穩定運行。
在雜訊整形的實現上，採用了由浮動式反向器放大器構成的動態放大器，此設計不僅提供更為激進的雜訊轉移函數，還進一步降低了功耗。在10MHz取樣頻率下，本設計目標達到超過12位元的有效位元（ENOB），預期頻寬為625KHz，使得在1080p、30幀/秒的影像感測應用中，每19條Column可共用一顆ADC，大幅降低功耗與佈局面積需求。
本論文電路是在TSMC 90nm 1P9M CMOS製程下實現，晶片總面積包含TSMC的 ESD I/O pad為1.361×1.102 mm2，核心電路面積為0.887×0.667 mm2。此類比數位轉換器的供應電壓為1.2V、取樣頻率10 MHz。模擬在頻寬為625KHz時有效位元（ENOB）為13.43bits、頻寬為312.5KHz時ENOB為14.57bits。在量測結果中，頻寬為625KHz時有效位元（ENOB）為12.21bits、頻寬為312.5KHz時ENOB為13.91bits。

This study proposes a high-precision, low-power ADC architecture for the back-end of CMOS image sensors, aiming to overcome the limitations of traditional Single Slope (SS) ADCs in resolution and speed, thereby meeting the demands of high-resolution image sensing. To address the dual requirements of accuracy and power consumption, this design employs a Vcm-based conversion approach and incorporates error modulation techniques to effectively suppress errors caused by capacitor array mismatches during the manufacturing process. Additionally, to mitigate the issue of kickback noise affecting the architecture, a low-kickback noise comparator is introduced, ensuring stable system operation.
For noise shaping, a dynamic amplifier composed of a floating inverter amplifier is utilized. This design not only offers a more aggressive noise transfer function but also further reduces power consumption. At a sampling frequency of 10 MHz, the proposed design targets an effective number of bits (ENOB) exceeding 12 bits with an expected bandwidth of 625 KHz. This allows each ADC to be shared among 19 columns in 1080p, 30 fps image sensing applications, significantly reducing power consumption and layout area requirements.
The circuit in this work is implemented using the TSMC 90nm 1P9M CMOS process. The total chip area, including the TSMC ESD I/O pads, is 1.361 × 1.102 mm², while the core circuit area is 0.887 × 0.667 mm². This analog-to-digital converter operates at a supply voltage of 1.2V and a sampling frequency of 10 MHz. Simulations show an ENOB of 13.43 bits at a bandwidth of 625 KHz and 14.57 bits at 312.5 KHz. Measured results indicate an ENOB of 12.21 bits at 625 KHz and 13.91 bits at 312.5 KHz.

[1] Wu, J.-T., Analog-Digital Interfaces. Data-Conversion Integrated Circuits, April
29, 2020.
[2] ISSCC 2022 Short Course SC1：Introduction to ADCs DACs
[3] B. Murmann, "ADC Performance Survey 1997-2021," [Online].
Available:http://web.stanford.edu/~murmann/adcsurvey.html.
[4] L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021.
[5] Razavi, B., The Bootstrapped Switch [A Circuit for All Seasons], in IEEE Solid-State Circuits Magazine. Summer 2015. pp. 12-15.
[6] Y. Zhu et al., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010.
[7] Y. Huang, H. Schleifer and D. Killat, "Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs," in European Conference on Circuit Theory and Design (ECCTD), Dresden, Germany, 2013.
[8] X. Tang et al., "An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, April 2020.
[9] X. Tang et al., "A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3248-3259, Dec. 2020.
[10] Y. -S. Shu, L. -T. Kuo and T. -Y. Lo, "An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016.
[11] J. S. Yoon, J. Hong, and J. Kim, “A digitally-calibrated 70.98dBSNDR 625kHz-bandwidth temperature-tolerant 2nd-order noiseshaping SAR ADC in 65nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), 2019.
[12] H. Zhuang et al., "A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting," in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1636-1647, June 2019.
[13] T. -H. Wang, R. Wu, V. Gupta, X. Tang and S. Li, "A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation," in IEEE Journal of Solid-State Circuits, vol. 56, no. 12, pp. 3668-3680, Dec. 2021.
[14] Q. Zhang et al., "A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration," in IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2181-2195, July 2022.
[15] C. -C. Chen, Y. -H. Huang, J. C. J. S. Marquez and C. -C. Hsieh, "A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive Voltage– Time–Voltage Converter," in IEEE Journal of Solid-State Circuits, vol. 58, no. 10, pp. 2897-2906, Oct. 2023.
[16] Jie Sun,Weiqiang Liu,Xin Li,Chenggang Yan.Attenuation-factor Error Shaping Technique for Split CDAC in SAR ADCs.[J]:Electronics Letters,2020,56(8)
[17] Y. Chen et al., "Split capacitor DAC mismatch calibration in successive approximation ADC," 2009 IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2009, pp. 279-282.