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研究生: 顏偉倫
Yen, Wei-Luen
論文名稱: 超高效能H.264視訊解碼器在嵌入式多核心平台上之平行化設計
A High Performance Parallelism of H.264 Video Decoder on Embedded Multi-core Platform
指導教授: 石維寬
Shih, Wei-Kuan
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 55
中文關鍵詞: H.264解碼器平行化方法嵌入式系統多核心
外文關鍵詞: H.264 Decoder, Parallelism, Embedded System, Multi-core
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  • 隨著科技的進步,近幾年發展出許多高複雜度及需要大量資料運算的應用程式來滿足人們的需求,例如影音的編解碼器(Video/Audio Encoder/Decoder)、3D物理模擬(3D Physical Simulation)、數位訊號處理(Digital Signal Processing)、網路(Network)…等,然而伴隨著可攜式裝置的普及,這些需求進一步從一般個人電腦衍伸到嵌入式系統上,人們想要利用這些可攜式裝置來滿足個人娛樂的需求,從基本的聽音樂、上網,到進階的影音播放,例如播放高解析度的影片。

    H.264/AVC是目前廣受歡迎的一套視訊編解碼標準,由ITU-T(國際電信聯盟)中的視訊編碼專家組(VCEG)和ISO/IEC運動圖像專家組(MPEG)聯合的聯合視訊組(JVT,Joint Video Team)所提出的高度壓縮數位視訊編解碼標準。這種編碼技術也被稱為AVC(Advanced Video Coding)。第一版標準於2003年5月完成,近來常被運用在高解析度影像(HD Video、HDTV)的編解碼方面。

    現今的系統已漸漸走向使用多核心處理器的趨勢,因為不斷提高單顆核心的頻率不僅得不到預期的效能提升,在耗電量方面也是相當驚人,反觀使用多顆低頻率的核心卻可以在效能提升及降低耗電量方面都有優異的表現,尤其在嵌入式方面,使用多核心已是許多系統廠商的最佳選擇。

    本篇論文最主要是在說明如何在嵌入式多核心平台上為H.264/AVC解碼器設計一種平行化的架構,與以往單純只使用Data Partitioning及Function Partitioning的平行方式不同,我們使用了一種混合型式的平行方法,並搭配為此平行化架構設計的優先權動態排程機制來提升平行度,使其在解碼高解析度(Full HD)影片時,能充分利用嵌入式多核心上的核心資源,達到高效能的訴求。因其為嵌入式多核心系統設計,使用fine-grained的MB-level Parallelism而非使用其它coarse-grained的Parallelism,例如GOP-level Parallelism,這樣可以減少大量使用記憶體,符合嵌入式系統的設計需求。

    經由模擬結果發現,我們提出的H.264解碼器平行化設計,與其他Spatial Domain的平行化設計,例如2D-Wave Parallelism及 Pipeline+2D Wave Parallelism相比,更能接近最佳的Speed-up理想值,並能解決核心之間Load Balance的問題。


    中文摘要 Abstract 致謝 目錄 圖目錄 表目錄 1 Introduction 1.1 Background 1.2 Motivation 1.3 Reading Guidance 2 H.264/AVC Standard 2.1 H.264/AVC Introduction 2.2 Hierarchy of a Video Sequence 2.3 H.264/AVC Codec 2.4 H.264/AVC Structure 2.4.1 Profiles and Levels 2.4.2 Reference Pictures 2.4.3 Slices 2.4.4 Macroblock Prediction 2.5 Decode Processing 2.5.1 Intra Prediction 2.5.2 Inter Prediction 2.5.3 Deblocking Filter 2.5.4 Transformation and Quantization 2.5.5 Reorder 2.5.6 Entropy Coding 3 H.264 Decoder Parallelism Overview 3.1 Function Partitioning 3.2 Data Partitioning 3.2.1 GOP-level Parallelism 3.2.2 Frame-level Parallelism 3.2.3 Slice-level Parallelism 3.2.4 MB-level Parallelism 3.2.4.1 2D-Wave Parallelism 4 Parallel Strategy and Execution Model 4.1 Parallel Strategy - Task Pool Algorithm 4.2 Execution Model 4.2.1 The Flow of Execution Model 4.2.2 Inter Table 4.2.3 IQ/IT Priority Table 4.2.4 MC Finished Table 4.2.5 DF Finished Table 4.2.6 Priority-driven Dynamic Scheduling 4.2.7 Priority Policy 5 Simulation Result and Analysis 5.1 Scalability Analysis for Various Parallelism 5.1.1 2D-Wave Parallelism 5.1.2 Pipeline+2D-Wave Parallelism 5.1.3 Proposed Parallelism 5.2 Simulation Result 5.2.1 Simulation for Full HD with Identical Execution Time 5.2.2 Simulation for Full HD with Distinct Execution Time 6 Conclusion 7 Future Work Reference

    [1] Joint Video Team of ITU-T and ISO/IEC JTC 1, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC)”, Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, March 2003

    [2] Erik B. van der Tol, Egbert G. Jaspers, Rob H. Gelderblom, “Mapping of H.264 decoding on a multiprocessor architecture”, Proceedings of SPIE, Vol. SPIE-5022, pp. 707-718, May 2003

    [3] Cor Meenderinck, Arnaldo Azevedo, Ben Juurlink, Mauricio Alvarez Mesa, Alex Ramirez, “Parallel Scalability of Video Decoders, Journal of Signal Processing Systems”, Vol. 57, No. 2, pp. 173-194, November 2009

    [4] C. C. Chi, “Parallel H.264 Decoding Strategies for Cell Broadband Engine, Faculty of Electrical Engineering”, Mathematics and Computer Science, Delft University of Technology, Netherlands, February 2010

    [5] Yen-Chiu Chen, Hong-Rong Hsu, Wei-Luen Yen, Wei-Nung Su, Hsin-Wen Wei, Wei-Kuan Shih, “A Multi-Threading Framework for H.264 Decoder on ARM MPCore Platform”, The 20th VLSI Design/CAD Symposium, August 2009

    [6] X. Zhou, E. Q. Li, and Y.-K. Chen, Implementation of H.264 Decoder on General-Purpose Processors with Media Instructions, Image and Video Communications and Processing, Proceedings of the SPIE, Vol.5022, pp. 224-235, May 2003

    [7] Mauricio Alvarez Mesa, Alex Ramirez, Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Mateo Valero, “Scalability of Macroblock-level Parallelism for H.264 Decoding, Proceedings of the 2009 15th International Conference on Parallel and Distributed Systems, pp. 236-243, 2009

    [8] Iain E. G. Richardson, “H.264 and MPEG-4 Video Compression - Video Coding for Next-generation Multimedia”, John Wiley & Sons Press, March, 2005

    [9] Kue-Hwan Sihn, Hyunki Baik, Jong-Tae Kim, Sehyun Bae, Hyo Jung Song, “Novel Approaches to Parallel H.264 Decoder on Symmetric Multicore Systems”, 2009 IEEE International Conference on Acoustics, Speech and Signal Processing, 2009

    [10] Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramirez, Mateo Valero, “Parallel H.264 Decoding on An Embedded Multicore Processor”, High Performance Embedded Architectures and Compilers Fourth International Conference, January 2009

    [11] A. Azevedo, B.H.H. Juurlink, C.H. Meenderinck, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramirez, M. Valero, “A Highly Scalable Parallel Implementation of H.264”, Transactions on High-Performance Embedded Architectures and Compilers, Vol. 4, Issue 2, September 2009

    [12] M. Alvarez, A. Ramirez, M. Valero, A. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, “Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture”, Proceedings of the 4CCC: 4th Colombian Computing Conference, April 2009

    [13] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, Ajay Luthra, “Overview of the H.264/AVC Video Coding Standard”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, NO. 7, July 2003

    [14] ARM11 MPCore Processor http://www.arm.com/products/processors/classic/arm11/arm11-mpcore.php

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