本篇研究使用具高介電常數的超晶格氧化鉿鋯薄膜(SL-HZO)作為閘極介電層的材料，並以超晶格矽/矽鍺堆疊作為通道。由於超晶格氧化鉿鋯薄膜在特定退火溫度以及膜層厚度下會呈現晶相邊界狀態，在此狀態下薄膜會有較高的介電常數，以及較低的等效氧化層厚度(EOT)。除了可以提升驅動電流以外亦可以在物理上保持一定的氧化層厚度降低閘極漏電流。在通道的使用上選擇矽鍺/矽超晶格堆疊通道，藉由磊晶時矽鍺與矽之晶格常數不同所造成的應力提升通道的載子遷移率。除此之外採用環繞式閘極結構提升閘極的控制能力，降低漏電流。結合以上閘極氧化層，通道材料與結構之選擇有助於電晶體尺寸之微縮。
第一部分為金屬-絕緣層-金屬結構之電容，首先絕緣層的選擇是改變超晶格氧化鉿鋯每層的厚度，分別為每層0.5奈米，每層0.8奈米以及每層1.3奈米。而在退火溫度上分別進行450°C/550°C/650°C/750°C的退火，總計12種條件。經過電性的比較，每層0.5奈米，退火450°C的條件下具有最高的介電常數，在P-V的圖形上也呈現晶相邊界的圖形，也就是鐵電相與反鐵電相的混和圖形。
第二部分為超晶格氧化鉿鋯矽鍺/矽堆疊之環繞式閘極電晶體之研究。分別比較以超晶格氧化鉿鋯與氧化鉿作為閘極介電層之環繞式閘極電晶體。以超晶格氧化鉿鋯作為閘極氧化層的電晶體具有較高的開關電流比(ION/ IOFF)達到1.14×107，同時在平均次臨界擺幅的表現上也優於氧化鉿環繞式閘極電晶體。在驅動電流的表現上，超晶格氧化鉿鋯環繞式閘極電晶體的驅動電流約為氧化鉿環繞式閘極電晶體的兩倍。此外，在CMOS(互補式金屬氧化物半導體)反相器測量中，超晶格氧化鉿鋯環繞式閘極電晶體CMOS具有良好的VTC曲線，電壓增益達到84.99 V/V，在表現上都較氧化鉿環繞式閘極電晶體CMOS優異。
從上述結果來看，使用超晶格氧化鉿鋯作為矽鍺/矽堆疊之環繞式閘極電晶體的閘極介電層可以有效提升驅動電流，開關電流比(ION/ IOFF)以及降低次臨界擺幅(S.S.)。在反相器的運用上也有優異的表現，同時也與現今CMOS製程平台具有高度的兼容性。

The study applied superlattice hafnium zirconium oxide (SL-HZO) thin films with high dielectric constants as gate dielectric materials and used superlattice silicon/silicon-germanium stacks structure as the channel. Due to the Morphotropic phase boundary state of SL-HZO films at specific annealing temperatures and film thicknesses, the films exhibit higher dielectric constants and lower equivalent oxide thickness (EOT). This not only enhances the drive current but also physically maintains a certain oxide layer thickness to reduce gate leakage current. For the channel, silicon-germanium/silicon superlattice stacks are chosen to increase carrier mobility through the stress induced by the lattice constant difference between silicon-germanium and silicon during epitaxy. Additionally, gate-all-around structure is adopted to improve gate control ability and reduce leakage current. The combination of the above choices of gate oxide layer, channel material, and structure contributes to the scaling of transistors.
The first part involves the capacitor of the metal-insulator-metal structure. The choice of the oxide layer is to vary the thickness of each layer of the superlattice hafnium zirconium oxide, specifically 0.5 nm, 0.8 nm, and 1.3 nm per layer. Annealing is performed at temperatures of 450°C, 550°C, 650°C, and 750°C, resulting in total 12 conditions. After comparing the electrical properties, the condition of 0.5 nm per layer with 450°C annealing exhibits the highest dielectric constant. In the P-V graph, it also shows the Morphotropic phase boundary pattern, which is a mixed pattern of ferroelectric and antiferroelectric phases.
The second part focuses on the study of silicon-germanium/silicon stack gate-all-around (GAA) transistors with superlattice hafnium zirconium oxide. It compares GAA transistors using SL-HZO and HfO2 as the gate dielectric layer. Transistors with SL-HZO as the gate oxide exhibit a higher on/off current ratio (ION/IOFF) reaching 1.14×107. Additionally, they perform better in terms of average subthreshold swing compared to HfO2 GAA transistors. In terms of drive current performance, the drive current of SL-HZO GAA transistors is about twice that of HfO2 GAA transistors. Furthermore, in CMOS (complementary metal-oxide-semiconductor) inverter measurements, the SL-HZO GAA transistor CMOS shows a good VTC curve with a voltage gain of 84.99 V/V, outperforming the HfO2 GAA transistor CMOS in all aspects.
Based on the above results, using SL-HZO as the gate oxide for silicon-germanium/silicon stack gate-all-around (GAA) transistors can effectively enhance the drive current, increase the on/off current ratio (ION/IOFF), and reduce the subthreshold swing (S.S.). It also exhibits excellent performance in inverter applications and is highly compatible with current CMOS process platforms.

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