研究生: |
詹孟學 Meng-Syue Chan |
---|---|
論文名稱: |
在系統級封裝設計方法下的測試議題 The Testing Issues on System-in-Package Design Methodology |
指導教授: |
王俊堯
Chun-Yao Wang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 英文 |
論文頁數: | 25 |
中文關鍵詞: | 系統級封裝測試 、組合 、經濟 |
相關次數: | 點閱:1 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在系統級封裝設計方法中提供了在一個封裝中整合數個來自不同晶片供應商的裸晶的方案。相較於印刷電路和系統單晶片,在系統級封裝的設計方法中我們能夠獲得許多好處,像是降低開發成本、低耗電量、縮短開發時間和擁有較小的產品體積等優點。但是在系統級封裝的設計方法下也遭遇到了許多挑戰,在本篇論文中我們將討論兩個在系統級封裝設計方法下的測試議題。首先在論文中,將會探討系統級封裝的品質和成本的關係。在此部份我們會提出一個評估模型,藉此來找出在成本限制條件或是品質要求條件下的一組可行最佳解。而在決定系統的組成元件後,我們將針對系統級封裝的低組裝良率的問題,提出一個在沒有邊界掃瞄機制的晶片中測試內部連結的方法。
References
[1] M. Abadir, \Economics Modeling of Multichip Modules Testing Strategies,"
IEEE Transactions on Components, Packaging, and Manufacturing Technology,
vol. 21, no. 4, pp. 360-370, Nov, 1998.
[2] D. Appello, P. Bernardi, M. Grosso, and M. S. Reorda, \System-in-Package
Testing: Problems and Solutions," IEEE Design and Test of Computers, vol. 23,
no. 3, pp. 203-211, May/Jun, 2006.
[3] F. Corsi, S. Martino, and T. W. Williams, \Defect Level As a Function of Fault
Coverage and Yield," in Proc. European Test Conference, pp. 507-508, 1993.
[4] V. K. Kim, T. Chen, and M. Tegetho, \ASIC Manufacturing Test Cost Pre-
diction at Early Design Stage," in Proc. International Test Conference, pp. 356-
361, 1997.
[5] S.-K. Lu, T.-Y. Lee, and C.-W. Wu, \A Prot Evaluation System (PES) for
Logic Cores at Early Design Stage," in Proc. International Conference on Elec-
tronics, Circuits and Systems, vol. 3, pp. 1491-1494, 2001.
[6] B. McCarey, \Exploring the Challenges in Creating a High-quality Main-
stream Design Solution for System-in-Package (SiP) Design," in Proc. Inter-
national Symposium Quality of Electronic Design, pp. 556-561, 2005.
[7] A. A. Setty, H. L. Martin, \BIST and Interconnect Testing with Boundary
Scan," in Proc. Southeastcon, vol. 1, pp. 12-15, Apr, 1991.
[8] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha,
H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, \SIS:
24
A System for sequential circuit synthesis, Technical Report UCB/ERL M92/41,
Electronics Research Lab, Univ. of California, Berkeley, CA 94720, 1992.
[9] K. L. Tai, "System-In-Package (SiP): Challenges and Opportunities," in
Proc. Asia and South Pacic Design Automation Conference, pp. 191-196, 2000.
[10] E. J. Vardaman, \Is a Known Good Die Hard to Find?," in Proc. IEEE Multi-
Chip Module Conference, pp. 8, 1996.
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