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研究生: 許廷碩
Hsu, Ting-Shuo
論文名稱: 動態電壓頻率調整之電子系統層多核心模擬平台與軟體通訊應用程式介面
A DVFS Many-core ESL Simulation Platform with Software Communication API
指導教授: 劉靖家
Liou, Jing-Jia
口試委員: 陳添福
黃稚存
黃俊達
劉靖家
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 100
語文別: 英文
論文頁數: 59
中文關鍵詞: 電子系統層多核心
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  • 因為耗能效率(power efficiency),可擴展性(scalability) 和可調整性(adaptability),多核心(multi-/many-core)系統已經成為近來之趨勢。當設計一多核心系統之初期,電子系統層(electronic system level, ESL)模型經常用來模擬多核心系統。透過提高抽象層級(abstraction level)隱藏系統複雜的細節,電子系統層模擬技術相當適合用於系統早期的架構探索(architecture exploration)以及軟硬體共同設計(hardware/software co-design)。
    在這篇論文中,我們用SystemC語言建立了一個電子系統層之多核心模擬平台。此模擬平台包含十六顆處理元件(processing element)核心,並使用晶片上網路(network-on-chip, NoC)作為連結。我們也設計了一組軟體通訊應用程式介面(application programming interface, API),提供給軟體開發者撰寫可執行於此多核心模擬平台之平行化程式。我們會展示實際平行程式執行的性能分析,以及我們通訊應用程式介面的傳輸效率。
    此外,我們將上述之電子系統層多核心模擬平台修改為一個廣域非同步區域同步(globally-asynchronous locally-synchronous, GALS)系統,每個處理元件、每個晶片上網路之交換器(switch)、每個網路介面單元(network interface unit)都可以執行於不同的時脈週期。同時我們也在此模擬平台建立了功率模型,因此我們可用以模擬動態電壓頻率調整(dynamic voltage and frequency scaling, DVFS)下系統之性能與功率消耗。


    Contents 1 Introduction 8 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Background 10 2.1 SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 OSCI TLM-2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 ArchC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 OpenRISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 Open Core Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 Arteris NoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Proposed ESL Many-core Platform 16 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Network-on-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Processing Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 Architecture of Processing Elements . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 ESL Modeling for Processing Elements . . . . . . . . . . . . . . . . . . . 22 3.5 Inter-PE Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.1 Burst-mode Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.2 Single-mode Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6 Communication Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.1 PE-to-PE Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.2 DMA Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7 Software Communication Library . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7.1 Communication API for PE-to-PE . . . . . . . . . . . . . . . . . . . . . . 30 3.7.2 Communication API for DMA . . . . . . . . . . . . . . . . . . . . . . . . 30 4 DVFS Framework and Power Modeling 32 4.1 Multiple Clock Domain Framework . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Power Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.1 PE Power Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.2 NoC Power Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3 Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4 Voltage Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 Experimental Results 39 5.1 Communication Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2.1 Odd-Even Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.2 JPEG Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2.3 Object Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3 Power Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6 Conclusions and Future Work 55 6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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