研究生: |
楊晉杰 Chin Chieh yang |
---|---|
論文名稱: |
金屬/鐵電層/絕緣層/矽 結構電容與電晶體之試製與電性分析 The electrical properties of metal-ferroelectric-insulator-silicon(MFIS)capacitors and transistors using HfO2 andLa2O3 as gate dielectric layers |
指導教授: |
李雅明
Joseph Ya-Min Lee |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2005 |
畢業學年度: | 93 |
語文別: | 中文 |
論文頁數: | 83 |
中文關鍵詞: | 鐵電層 、絕緣層 、電晶體 、電容 |
相關次數: | 點閱:2 下載:0 |
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我們以射頻磁控濺鍍法製備金屬-鐵電(鋯鈦酸鉛)-絕緣層-半導體電容。本實驗採用兩種不同絕緣層(insulator) La2O3與HfO2,以射頻磁控濺鍍法方式,沉積不同厚度的絕緣層(insulator)當作緩衝層(buffer layer)。而後經由不同溫度的熱退火處理後,再以射頻磁控濺鍍法沈積PZT,最後再以lift-off的方式製作上電極,由此完成樣品的製作。自發性極化的特性是鐵電材料應用於非發揮性記憶體的主要精神,故本實驗主要是藉由電容-電壓以及電流-電壓的量測探討鐵電材料在其中所扮演的角色。
在本實驗中我們成功的製作金屬/鐵電薄膜(PZT)/絕緣體(La2O3、HfO2)/半導體(p-Si)電容器,並對其電性作分析,由電容-電壓的量測結果,我們可發現其C-V曲線走向在掃瞄振幅電壓小於6V時為順時針走向,而在掃瞄振幅電壓大於6V時為逆時針走向,這表示在當外加電壓小於6V時,C-V走向是鐵電極化在主導;當外加電壓大於6V時,電荷注入的影響大於鐵電極化,因此C-V走向是電荷注入在主導。
我們同時發現不同的絕緣層對記憶窗有很大的影響,因為不同的絕緣層會對不同的氧化曾電荷有不同的影響,氧化層電荷對記憶窗有很大的關聯,本實驗我們發現La2O3的氧化電荷為介面陷住電荷,而
HfO2為固定氧化層電荷。
我們進ㄧ步用La2O3為絕緣層來製作電晶體,可是卻沒有很好的記憶體的特性,可能是製程上有需要做進ㄧ步的改進。
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