應用於高速傳輸之寬頻電流型邏輯傳輸介面設計

簡易檢索 / 詳目顯示

回結果列表

研究生：	任致賢 Chih-Hsien Jen
論文名稱：	應用於高速傳輸之寬頻電流型邏輯傳輸介面設計 A 10Gb/s Wide-Band Current-Mode Logic I/O Interface of High-Speed Interconnect in 0.18um Technology
指導教授：	許雅三 YarSun Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	109
中文關鍵詞：	高速傳輸、寬頻、電流型邏輯、傳輸介面、限制放大器
外文關鍵詞：	10 Gb/s, wide-band, current-mode logic, cml, I/O, high-speed interconnect, cmos 0.18, limiting amplifier
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

近幾年來，由於處理器運算速度越來越快，單位時間所處理的資料日益增多，因此為了達到高速的電腦資料傳輸，我們需要一個能傳輸高速資料的介面，並能兼顧到低功率消耗與減小晶片面積的考量。在此論文中我們利用許多提高頻寬的技術結合電流型邏輯(Current-Mode Logic)電路，來設計此高速的傳輸介面，這些技術包括PMOS主動負載;負回授加上電流緩衝電晶體以及Miller電容，由於採用這些高頻寬技術，將傳統電流型邏輯電路演變為可操作在高速的架構，並得到跟使用實際電感所得到一樣高頻寬的效果，但是卻只需要較低的功率消耗，並減少80%以上的晶片面積。

在本論文中的傳輸介面的主要架構分為輸入端與輸出端的介面，在輸入端包括一個輸入訊號等化器(Equalizer)、輸入電壓限制放大器(Limiting Amplifier)以及電流型邏輯緩衝級電路(CML Buffer)。而在輸出端則包括三級架構的電流型邏輯緩衝級電路(CML Buffer)和輸出訊號預加強電路(Pre-emphasis Circuit)。全部的設計建立在台積電所提供TSMC 0.18um CMOS製程並進行下線，設計結果顯示此傳輸介面傳輸速度可隨所需要的速度調整輸出波形，最快速度可至10Gb/s，全部的消耗功率為70mW，而輸入端與輸出端layout面積分別為0.02mm²和0.008 mm²，並且在輸入端可以達到40dB input dynamic range與4mV input sensitivity，使得此限制放大器可以接收振幅為0.4mV~1.8V的訊號，並可以將其訊號完整傳至下級電路，如CDR。

The ever-increasing processing speed of microprocessor motherboards, optical transmission links, intelligent hubs and routers etc., is pushing the off-chip data rate into the gigabits-per-second range. CML I/O interfaces are becoming more and more popular with applications involving transceiver reaching data rates up to 2.5Gb/s or greater. The serial interconnect signals show a lot of high frequency attenuation, skin loss after propagation through long PCB trace on the backplane. At the transmitter, pre-equalizers alter the waveform due to low-pass response of the interconnect. Limiting Amplifiers (LA) are responsible to amplify the input signal to a sufficient voltage for the reliable operation of Clock Data Recovery (CDR).

We deploy the current mode logic to implement a low power, area-efficient 10 Gb/s wide-band current-mode logic (CML) I/O interface for high-speed interconnect. This I/O interface consists of an input equalizer, a limiting amplifier, a CML output buffer and an output voltage-peaking circuit. Several wide-band techniques for this work are adopted to broaden the bandwidth and realize the circuit in 10Gb/s operation. The techniques include PMOS active load inductive-peaking, negative active feedback, Miller capacitances and Cherry-Hooper topology. These techniques can reduce 80% of the circuit area compared to the circuit area with on-chip inductors. The integration of the input equalizer and output voltage-peaking is also verified in this paper to provide robust I/O interface for high-speed interconnect and compensate transmission signal attenuation in the backplane. This work has been implemented in a 0.18um CMOS technology. The total power consumption of the I/O interface is only 70mW. The areas of the input and output interface are 0.02mm² and 0.008mm². The input interface can operate at 10Gb/s with 40dB input dynamic range and 4mV input sensitivity.

Contents

List of Figures                                                        vii
List of Tables                                                         xii
1  Introduction                                                       1
1.1  High-Speed Transceiver Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2  Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3  Overview of Thesis Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2  Background                                                        4
2.1  High-Speed Network Switch Fabric IC Architecture . . . . . . . . . . . . . . . . . . . .4
2.2  Overall I/O Interface of Switch Fabric IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3  Evolution of Transceiver Techniques                                   9
3.1  Transistor-to-Transistor Logic (TTL) Technique . . . . . . . . . . . . . . . . . . . . . .10
3.2  Emitter Coupled Logic Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3  Low-Voltage Differential Signaling (LVDS) Technique . . . . . . . . . . . . . . . . 15
3.4  Current-Mode Logic Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5  Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4  Wide-Band Techniques for CML I/O                                  23
4.1  Current-Mode Logic Structure With PMOS Active Load . . . . . . . . . . . . . . . 23
4.2  Active Negative Feedback With Current Buffers . . . . . . . . . . . . . . . . . . . . . .34
4.3  Negative Miller Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.4  Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
5  Current-Mode Logic Input Interface                                  41
5.1  CML Input Interface Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.2  Input Equalizer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3  CML Basic Circuit for CML Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4  Gain Stage Amplifier Circuit With Active Feedback . . . . . . . . . . . . . . . . . . . 46
5.5  Bandgap Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6  Current-Mode Logic Output Interface                                51
6.1  CML Output Interface Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2  CML Basic Circuit for CML Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3  The Voltage-Peaking Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.4  Bandgap Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7  Experimental Results                                               58
7.1  Layout of the CML I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.2  Experimental Results of the CML Input Interface . . . . . . . . . . . . . . . . . . . . . 61
7.2.1  Input Equalizer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2.2  CML Basic Circuit for CML Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.2.3  Gain Stage Amplifier Circuit With Active Feedback . . . . . . . . . . . . . .66
7.2.4  Overall of the CML Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.2.5  Bandgap Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.3  Experimental Results of the CML Output Interface . . . . . . . . . . . . . . . . . . . . 70
7.3.1  CML Basic Circuit for CML Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.3.2  The Voltage-Peaking Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.3.3  Overall of the CML Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . .72
8  Comparisons                                                      75
8.1  Comparisons in the CML Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.2  Comparisons in the CML Buffer
Between TSMC 0.18μm Process and UMC 0.18μm Process . . . . . . . . . . . . . 82
8.3  Comparisons Between this Work and the Other Recently Published Results .85
9  Integration of the Transmitter in Switch Fabric IC                      86
9.1  3.2Gb/s 20:1 CML Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
9.2  20:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.3  Phase-Lock Loop Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
9.4  Experimental Results of the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10  Conclusion and Future Work                                       96
10.1  Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.2  Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Bibliography                                                        101
Appendix                                                           105
2005 IEEE International SOC Conference Paper . . . . . . . . . . . . . . . . . . . . . . . . .106
















List of Figures

Figure 1-1   Block diagram of a typical transceiver interface for switch fabric system 2

Figure 2-1   The folded version two-stage load-balanced switch . . . . . . . . . . . . . . . . . 5
Figure 2-2   The 8x8 switch fabric architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 2-3   Overall architecture of I/O Interface for Switch Fabric IC . . . . . . . . . . . . 7

Figure 3-1   Circuit supply and signal levels of some I/O interface standard . . . . . . . .9
Figure 3-2   A commercial TTL NAND-gate circuit . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 3-3   An ECL NOR/OR logic gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 3-4   A simplified model of the LVDS interface . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3-5   Example of relation between the signal-ended output and the differential signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3-6   Block diagram of a basic differential architecture . . . . . . . . . . . . . . . . . .19
Figure 3-7   The voltage variations of the output nodes in terms of the differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 4-1   The different types of loads in the CML circuits . . . . . . . . . . . . . . . . . . .25
Figure 4-2   The CML circuit with PMOS active load . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4-3   The equivalent schemas of PMOS active load . . . . . . . . . . . . . . . . . . . . 26
Figure 4-4   Small signal model of PMOS active load . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4-5   The iD-VSD curves of PMOS active load . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 4-6   PMOS size vs. voltage-peaking ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 4-7   The ID-VSD curves of PMOS active load . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 4-8   Gate-voltage of PMOS vs. voltage-peaking ratio . . . . . . . . . . . . . . . . . . 30
Figure 4-9   Time domain waveform of active inductor control . . . . . . . . . . . . . . . . .32
Figure 4-10   Frequency response of active inductor control . . . . . . . . . . . . . . . . . . . 32
Figure 4-11  Time domain waveform of PMOS gate-voltage control . . . . . . . . . . . . . 33
Figure 4-12  Two stages of the tapered CML chain . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 4-13  The tapered CML circuits with active negative feedback . . . . . . . . . . . . 35
Figure 4-14  The tapered CML circuits with active negative feedback and current buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4-15  The equalizer circuit with active negative feedback and current buffers 37
Figure 4-16  Waveforms of the equalizer circuit with active feedback and current buffers @ 1Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 4-17  Waveforms of the equalizer circuit with active feedback and current buffers @ 10Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 4-18  Frequency response of the equalizer circuit with active feedback and current buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 4-19  The tapered CML circuits with negative-Miller capacitance . . . . . . . . . .39
Figure 4-20  Block diagram of overall architecture of the wide-band techniques . . . .40

Figure 5-1   Block diagram of the transceiver interface for the switch fabric system 42
Figure 5-2   Block diagram of input interface with equalizer . . . . . . . . . . . . . . . . . . .42
Figure 5-3   Block diagram of Equalizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 5-4   Block diagram of basic current-mode logic circuit . . . . . . . . . . . . . . . . .45
Figure 5-5   Time domain waveforms of active inductor control . . . . . . . . . . . . . . . . 46

Figure 5-6   Block diagram of four gain stages with a total feedback offset canceling network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 5-7   Block diagram of CML gain-stage circuit . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 5-8   Block diagram of bandgap voltage reference circuit . . . . . . . . . . . . . . . .50

Figure 6-1   Block diagram of the transceiver interface for the switch fabric system 52
Figure 6-2   Block diagram of output interface with voltage-peaking circuit . . . . . . .52
Figure 6-3   Block diagram of basic current-mode logic circuit . . . . . . . . . . . . . . . . .54
Figure 6-4   Waveforms of active inductor control (the size of PMOS) . . . . . . . . . . . 54
Figure 6-5   Block diagram of voltage-peaking circuit . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 6-6   Block diagram of the differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 6-7   The waveforms of the voltage-peaking circuit . . . . . . . . . . . . . . . . . . . . 56
Figure 6-8   Block diagram of bandgap voltage reference circuit . . . . . . . . . . . . . . . .57

Figure 7-1   Layout of the CML input interface. core circuit area : 0.02mm² . . . . . . 59
Figure 7-2   Layout of the CML output buffer. core circuit area : 0.004mm² . . . . . . 59
Figure 7-3   Layout of the CML output interface. core circuit area : 0.008mm² . . . . 60
Figure 7-4   Chip layout of the CML input interface. core circuit area : 0.02mm² . . 60
Figure 7-5   Frequency response of equalizer circuit with NMOS control . . . . . . . . .61
Figure 7-6   Frequency response of equalizer circuit with NMOS control . . . . . . . . .62
Figure 7-7   Waveforms of input signal with and without equalizer . . . . . . . . . . . . . .62
Figure 7-8   Simulated response of the receiver interface . . . . . . . . . . . . . . . . . . . . . 63
Figure 7-9   Time domain waveforms of active inductor control . . . . . . . . . . . . . . . . 64
Figure 7-10  Frequency response of active inductor control . . . . . . . . . . . . . . . . . . . . 64
Figure 7-11  Waveforms of active inductor control (the size of PMOS) . . . . . . . . . . . 65
Figure 7-12  Frequency response of active inductor control (the size of PMOS) . . . . 65
Figure 7-13  Waveforms of a 4mV input signal amplified by the 4-stage gain amplifier with active feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 7-14  Waveforms of a 1.8mV input signal amplified by the 4-stage gain amplifier with active feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 7-15  Simulated response of the CML 4-stage amplifier + CML output buffer @ 10 Gb/s 27 – 1 PRBS input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 7-16  Simulated response of the overall CML input interface @ 10 Gb/s 231 – 1 PRBS input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 7-17  The simulated results of the bandgap voltage reference circuit in the variations of temperature and power supply . . . . . . . . . . . . . . . . . . . . . . 69
Figure 7-18  The waveforms of the voltage-peaking circuit . . . . . . . . . . . . . . . . . . . . 71
Figure 7-19  Simulated response of the transmitter buffer @ 10 Gb/s 231 – 1 PRBS input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 7-20  Waveforms of the CML output interface @ 5 Gb/s input data rate . . . . .73
Figure 7-21  Waveforms of the CML output interface @ 10 Gb/s input data rate . . . .73
Figure 7-22  Waveforms of the CML output interface with voltage-peaking circuit @ 10 Gb/s input data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 7-23  Simulated response of the CML output interface @ 10 Gb/s 27 – 1 PRBS input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 8-1   The current of current source varied the current source size (W) in TSMC 0.18μm process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 8-2   Waveforms of active inductor control (the size of PMOS) in TSMC 0.18μm process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 8-3   Frequency response of active inductor control (the size of PMOS) in TSMC 0.18μm process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 8-4   Layouts of the 3-stage and 5-stage CML output buffers . . . . . . . . . . . . .80
Figure 8-5   Waveforms of the 5-stage CML output buffer . . . . . . . . . . . . . . . . . . . . .81
Figure 8-6   Waveforms of the 3-stage CML output buffer . . . . . . . . . . . . . . . . . . . . .81
Figure 8-7   The current of current source varied the current source size (W) in TSMC 0.18μm and UMC 0.18μm process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 8-8   The output waveforms of the CML input interface in TSMC 0.18μm and UMC 0.18μm process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 9-1   A 3.2Gb/s 20:1 CML Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 9-2   Circuit topology of 20:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 9-3   2:1 Multiplexer and D-Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 9-4   Block diagram of phase-lock loop circuit . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 9-5   Block diagram of VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 9-6   Current mirror and one VCO delay stage . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 9-7   Block diagram of the Phase Frequency Detector . . . . . . . . . . . . . . . . . . .92
Figure 9-8   Block diagram of the Charge Pump and Low Pass Filter . . . . . . . . . . . . 92
Figure 9-9   4-phase PLL simulation, 32ps@1.6GHz . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 9-10  Waveforms of the transmitter at the output of CML buffer with 50Ω . 94
Figure 9-11  Eye diagram of the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Figure 9-12  The overall layout of the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 10-1  The architecture of a 2.56/3.2Gb/s dual mode 1:16/20 CML transceiver 98
Figure 10-2  Overall architecture of I/O Interfaces for Switch Fabric IC . . . . . . . . . . 99
Figure 10-3  The 8x8 switch fabric architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99




List of Tables

Table 3-1   Some recent applications of LVDS standard . . . . . . . . . . . . . . . . . . . . . . .16
Table 8-1   Performance of 5-stage and 3-stage CML output buffers . . . . . . . . . . . . .80
Table 8-2   Performance of CML I/O in TSMC 0.18μm and UMC 0.18μm process . 84
Table 8-3   Performance and comparison with other recently published results . . . . .85

                                

Bibliography

[1] “The Evolution of High-Speed Transceiver Technology”, Altera, 2002

[2] C. S. Chang, D. S. Lee and Y. S. Jou, “Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering,” Computer Communications, Vol. 25, pp. 611-622, 2002

[3] C. S. Chang, D. S. Lee and C. M. Lien, “Load balanced Birkhoff-von Neumann switch, part II: Multi-stage buffering,” Computer Communications, Vol. 25, 2002, pp. 623-634

[4] C. S. Chang, D. S. Lee, and C. Y. Yue, “Providing guaranteed rate services in the load balanced Birkhoff-von Neumann switches,” Proceedings of IEEE INFOCOM, 2003.

[5] C. S. Chang, D. S. Lee and Y. J. Shih, “Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets,” preprint, 2004.

[6] Fuji Yang; O'Neill, J.H.; Inglis, D.; Othmer, J., “A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network Ics”, Solid-State Circuits, IEEE Journal of Volume 37, Issue 12, Dec. 2002 Page(s):1813 - 1821

[7] “IEEE standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)”, IEEE Std 1596.3-1996 31 July 1996

[8] Elmasry, M.I.; Thompson, P.M., “Analysis of load structures for current-mode logic”, Solid-State Circuits, IEEE Journal of Volume 10, Issue 1, Feb 1975 Page(s):72 – 75

[9] Treadway, R.L., “DC analysis of current mode logic”, Circuits and Devices Magazine, IEEE Volume 5, Issue 2, March 1989 Page(s):21 - 35

[10] Payam Heydari, “Design Issues in Low-Voltage High-Speed Current-Mode Logic Buffers”, GLSVLSI’03, April 28-29, 2003.

[11] E. M. Cherry and D. E. Hooper, “The Design of Wide-Band Transistor Feedback Amplifier”, Inst. Elec. Eng. Proc., Vol. 110, No. 2, pp. 375-389, Feb. 1963.

[12] Song Liu and R. Jacob Baker, “Process and Temperature Performance of a CMOS Beta-Multiplier Voltage Reference”, Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on, IEEE.

[13] Chia-Hsin Wu; Jieh-Wei Liao; Shen-Iuan Liu, “A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors”, Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Volume 1, 23-26 May 2004 Page(s):I - 1044-7 Vol.1

[14] Paul Westergaard, Timothy O. Dickson, and Sorin P. Voinigescu, ”A 1.5V 20/30 Gb/s CMOS Backplane Driver with Digital Pre-emphasis”, Custom Integrated Circuits Conference, 2004.

[15] S. Galal, and B. Razavi, “10Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18µm CMOS Technology”, International Symposium on Solid-State Circuits Conference, pp. 188-189, Feb. 2003.

[16] Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, “A 10Gb/s Receiver with Equalizer and On-chip ISI Monitor in 0.11µm CMOS”, VLSI Circuits, 2004. Digest of Technical Papers.

[17] Rui Tao, Manfred Berroth, “10 Gb/s Limiting Amplifier for Optical links”, Solid-State Circuits Conference, 2003. ESSCIRC '03.

[18] Mataya, J.A.; Haines, G.W.; Marshall, S.B., ”IF Amplifier using Cc compensated transistors”, Solid-State Circuits, IEEE Journal of Volume 3, Issue 4, Dec 1968 Page(s):401 – 407

[19] “Transistor-to-Transistor Logic (TTL)”, www.play-hookey.com
[20] Dr. Maitham Shams, “CML building blocks for high frequency addition in VLSI”, High speed and Low Power VLSI design course, Monday March 24th, TB202

[21] P. Larsson, “A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability”, Solid-State Circuits, IEEE Journal of Volume 34, Issue 12, Dec. 1999.
[22] J.G. Manteatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, Solid-State Circuits, IEEE Journal of Volume 31, Issue 11, Dec. 1996.

[23] B. Razavi, “Design of Analog VMOS Integrated Circuits”, Mc.Graw-Hill. 2001

[24] Y. Guo, Z. Zhang, W. Hu, L. YANG, “CMOS MULTIPLEXER AND DEMULTIPLEXER FOR GIGABIT ETHERNET”, Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on Volume 1, 29 June-1 July 2002 Page(s):819 - 823 vol.1

[25] Lu Jianhua, Tian Lei, Chen Haitao, Xie Tinging, Chen Zhiheng, Wang Zhigong, “Design Techniques of CMOS SCL circuits for Gb/s Applications”, ASIC, 2001. Proceedings 4thInternational Conference on 23-25 Oct. 2001 Page(s):559 - 562

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文