隨著科技的發展，無線通訊技術大幅改善人們的生活，4G無線通訊提供了極高的資料傳輸速度，讓人們在通話時能夠享有更高的品質甚至透過視訊面對面通話，網路傳輸的速度能夠讓人們使用攜帶型裝置觀看高畫質的影片或是直播節目，而在這些美好的應用背後，類比數位轉換器是系統中不可或缺的，它是唯一能夠將大自然訊號轉換成數位訊號的電路，讓大自然訊號經由數位訊號處理得到更多的好處。現今許多不同類型的類比數位轉換器持續提升效能，往更高的解析度或是更高的速度發展，但是連續漸進式類比數位轉換器卻是最近較為流行的，因為它本身的面積與功耗較小，能夠藉由製程縮小獲得更快的速度，比其他類型的類比數位轉換器更有優勢。
本論文實現了一個高速帶冗餘位連續漸進式類比數位轉換器，在每秒一億次取樣的速度以及10位元的解析度下，考量電容不匹配與數位類比轉換器的穩定時間兩項非理想效應，計算出帶冗餘位演算法中每次切換的基底，這個10位元每秒一億次取樣的連續漸進式類比數位轉換器利用台積電65奈米的CMOS製程來設計，操作電壓為1V，軌對軌輸入訊號的振幅為1.9V，模擬結果中訊號與雜訊諧波比可達到62.09dB，相當於有效位元為10.02，DNL為+0.6/-0.4 LSB，INL為+0.63/-0.4 LSB，平均消耗功率為2.02 mW，整體面積約為0.28785 mm2。

The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales.
In the thesis, we have proposed a high speed SAR ADC with redundancy algorithm. The algorithm combines the criterion of capacitor mismatch and DAC settling time. The radix of each stage can be calculated precisely under 100 million samples per second. The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1V supply voltage. The full rail-to-rail input swing is 1.9V peak to peak. This design achieve signal to noise and distortion ratio of 62.09dB, equivalent to the effective number of bits 10.02.The peak DNL values are -0.4 to +0.6 LSB and the peak INL values are -0.4 to +0.63 LSB. The average power consumption is 2.02mW.

[1] J. McCreary and P. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques,” IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371–379, Dec. 1975.
[2] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599–606, May 1999.
[3] D. Aksin, M. Al-Shyoukh, and F. Maloberti, "Switch Bootstrapping for Precise Sampling Beyond Supply Voltage", IEEE Journal of Solid State Circuits, pp. 1938-1943, Aug.2006.
[4] G.Y. Huang, C.C. Liu, Y.-Z. Lin, and S.J. Chang, "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," in IEEE ASSCC Dig. Tech. Papers, pp. 157-160, November 2009.
[5] B. P. Ginsburg and A.P. Chandrakasan "An energy-efficient charge recyclingapproach for a SAR converter with capacitive DAC", Proc. IEEE Symp. Circuits Syst., pp.184 -187 2005
[6] C.C. Liu, et al, ‘‘A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,’’ IEEE J. Solid-State Circuits, vol.45, no. 4, Apr. 2010, pp. 731-740.
[7] S. Haenzsche, S. Henker, and R. Schuffny, “Modelling of Capacitor Mismatch and Non-Linearity Effects in Charge Redistribution SAR ADCs,” in Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Jun. 2010, pp. 300-305.
[8] T. Ogawa, H. Kobayashi, Y. Takahashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K. Yagi, T. Mori, "SAR ADC Algorithm with Redundancy and Digital Error Correction", IEICE Trans. Fundamentals, vol.E93-A, no.2 (Feb. 2010).
[9] T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, N. Takai, "SAR ADC Algorithm with Redundancy", IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, pp.268-271 (Dec. 2008).
[10] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007.
[11] Shuo-Wei Michael Chen et al, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13 μm CMOS” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.2669-2680, DECEMBER 2006
[12] P. M. Figueiredo and J. C. Vital, "Kickback noise reduction techniques for CMOS latched comparators", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.53, no.7, pp. 541-545, 2006.
[13] Yan Huang, H.Schleifer, and D.Killat, “Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs” Circuit Theory and Design (ECCTD), Sept. 2013.
[14] R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J.Sel. Areas Commun., vol. 17, no. 4, pp. 539-550, Apr. 1999.
[15] T. Waho, “Non-binary successive approximation analog-to-digital converters:A survey,” in Proc. IEEE Int. Symp. Multiple-Valued Logic(ISMVL), 2014, pp. 73–78
[16] B. Murmann, “On the use of redundancy in successive approximation A/D converters,” in Proc. IEEE Int. Conf. Sampling Theory and Applications (SampTA), 2013, pp. 1–4
[17] J. Yang, T. L. Naing and B. Brodersen, “A 1-GS/s 6-bit 6.7-mW ADC in 65nm CMOS,” IEEE Custom Integrated Circ. Conf. (CICC), pp. 287-290. 2009
[18] P. Harpe, et al, ‘‘A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS,’’ IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 388-389.
[19] H. Wei "An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistiveDAC", IEEE J. Solid-State Circuits, vol. 47, no. 11, pp.2763 -2772. 2012
[20] C.C. Liu, et al., “A 1-μW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,” IEEE J. Solid-State Circuits, pp. 2783-2795, Nov 2012.
[21] R. Kapusta et al., “A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3059–3066, Dec. 2013.
[22] H. Nakane, et al, “A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver,” IEEE J. Solid-State Circuits,vol. 49, no. 11, pp.2503 -2514. 2014
[23] B. Razavi, Design of Analog CMOS Integrated Circuit. Boston, MA: McGraw-Hill, 2001.
[24] P. E. Allen, CMOS Analog Circuit Design. New York:Oxford,2002