低功耗的應用使得超低電壓的操作越來越受歡迎，像是分散式微感測網路，植入性醫療裝置或是行動式電子器材。次臨界區的操作對於最終要求能由環境獲取能量以延長電池壽命的目標是個可能的解決方式。先前的文獻使用次臨界邏輯電路設計已經成功的實現在量測結果上。然而，次臨界區的操作使得電晶體的導通電流呈現與閘集電壓以及臨界電壓為指數變化的關係，而降低了系統對製程，電壓，溫度漂移的免疫力。

操作在次臨界區下，傳統六個電晶體的靜態隨機存取記憶體無法達到設計目標因為較差的讀取穩定度以及微弱的寫入性，這使得在製程，電壓，溫度漂移因素下難以達到取捨。本篇論文中，我們提出了以九個電晶體當作靜態隨機存取記憶體的記憶單元，有著切斷回授路徑的寫入以及無干擾的讀取的特色而達到次臨界區的操作。除此之外，為了增強此靜態隨機存取記憶體的可靠度，一些架構上的技巧也同時被採用，像是分割字組線，複製字元線，負電壓的字組線。一個由三千兩百字元組成的九個電晶體陣列使用了九十奈米互補金氧半技術製造出來。量測結果展示了此九個電晶體的記憶單元正確地操作在一百零五毫伏特以四百六十一千赫茲的速度。受惠於操作在一百零五毫伏特，此靜態隨機存取記憶體的操作功耗為六點九三微瓦而能量消耗為十六點四微微焦耳。

[1] H. Soeleman and K. Roy, “Ultra-low power digital subthreshold logic circuits,”
in Proceeding of International Symposium on Low Power Electronics and Design,
pp. 94–96, 1999.
[2] M.-E. Hwang, A. Raychowdhury, K. Kim, and K. Roy, “A 85mV 40nW Process-
Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology,” in IEEE Symposium
on VLSI Circuits Dig. Tech. Papers, pp. 154–155, June 2007.
[3] A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-threshold Design for Ultra
Low-Power Systems (Series on Integrated Circuits and Systems). Secaucus, NJ,
USA: Springer-Verlag New York, Inc., 2006.
[4] J. M. Rabaey, J. Ammer, T. Karalar, S. Li, B. Otis, M. Sheets, and T. Tuan, “Pi-
coRadios for Wireless Sensor Networks: The Next Challenge in Ultra-Low-Power
Design,” in IEEE International Solid-State Circuits Conference Dig. Tech. Papers,
February 2002.
[5] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli,
Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70MB SRAM in 65nm CMOS tech-
nology with integrated column-based dynamic power supply,” in IEEE International
Solid-State Circuits Conference Dig. Tech. Papers, pp. 474–611, Feb. 2005.
[6] M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada,
K. Yanagisawa, and K. Osadal, “A 300MHz 25mA/Mb leakage on-chip SRAM mod-
ule featuring process-variation immunity and low-leakage-active mode for mobile-
phone application processor,” in IEEE International Solid-State Circuits Conference
Dig. Tech. Papers, pp. 494–542, Feb. 2004.
[7] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge Uni-
versity Press, 2 ed., August 2009.
[8] T.-H. Kim, J. Keane, H. Eom, and C. Kim, “Utilizing Reverse Short-Channel Effect
for Optimal Subthreshold Circuit Design,” IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 15, pp. 821–829, July 2007.
[9] M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao,
S. Kayano, and T. Nakano, “A divided word-line structure in the static RAM and
its application to a 64K full CMOS RAM,” IEEE Journal of Solid-State Circuits,
vol. 18, pp. 479–485, Oct 1983.
[10] B. Amrutur and M. Horowitz, “A replica technique for wordline and sense control in
low-power SRAM’s,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1208–1219,
Aug 1998.
[11] H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, Y. Fujimura, K. Ando,
T. Kusunoki, K. Yamaguchi, and N. Homma, “A 1.8-ns access, 550-MHz, 4.5-Mb
CMOS SRAM,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1650–1658, Nov
1998.
[12] H. Tanaka, M. Aoki, T. Sakata, S. Kimura, N. Sakashita, H. Hidaka, T. Tachibana,
and K. Kimura, “A precise on-chip voltage generator for a gigascale DRAM with a
negative word-line scheme,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 1084–
1090, Aug 1999.
[13] H. Mizuno and T. Nagano, “Driving source-line cell architecture for sub-1-V
high-speed low-power applications,” IEEE Journal of Solid-State Circuits, vol. 31,
pp. 552–557, Apr 1996.
[14] E. Seevinck, F. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM
cells,” IEEE Journal of Solid-State Circuits, vol. 22, pp. 748–754, Oct 1987.
[15] K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Ko-
batake, “A read-static-noise-margin-free SRAM cell for low-VDD and high-speed
applications,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 113–121, Jan. 2006.
[16] L. Chang, D. Fried, J. Hergenrother, J. Sleight, R. Dennard, R. Montoye, L. Sekaric,
S. McNab, A. Topol, C. Adams, K. Guarini, and W. Haensch, “Stable SRAM cell
design for the 32 nm node and beyond,” in IEEE Symposium on VLSI Technology
Dig. of Tech. Papers, pp. 128–129, June 2005.
[17] B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm Sub-threshold SRAM
Design for Ultra-Low-Voltage Operation,” IEEE Journal of Solid-State Circuits,
vol. 42, pp. 680–688, March 2007.
[18] I. J. Chang, J.-J. Kim, S. Park, and K. Roy, “A 32 kb 10T Sub-Threshold SRAM
Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS,” IEEE
Journal of Solid-State Circuits, vol. 44, pp. 650–658, Feb. 2009.
[19] M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, and H. Shinohara, “A
45-nm 0.6V cross-point 8T SRAM with negative biased read/write assist,” in IEEE
Symposium on VLSI Circuits Dig. Tech. Papers, pp. 158–159, June 2009.
[20] T.-H. Kim, J. Liu, J. Keane, and C. Kim, “A 0.2 V, 480 kb Subthreshold SRAMWith
1 k Cells Per Bitline for Ultra-Low-Voltage Computing,” IEEE Journal of Solid-
State Circuits, vol. 43, pp. 518–529, Feb. 2008.
[21] A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A feasibility study of subthresh-
old SRAM across technology generations,” in IEEE International Conference on
Computer Design, pp. 417–422, Oct. 2005.
[22] M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanag-
isawa, and T. Kawahara, “90-nm process-variation adaptive embedded SRAM mod-
ules with power-line-floating write technique,” IEEE Journal of Solid-State Circuits,
vol. 41, pp. 705–711, March 2006.
[23] S. Mukhopadhyay, K. Kang, H. Mahmoodi, and K. Roy, “Reliable and self-repairing
SRAM in nano-scale technologies using leakage and delay monitoring,” in IEEE
International Test Conference, pp. 1126–1135, Nov. 2005.
[24] J. Kao, M. Miyazaki, and A. Chandrakasan, “A 175-mV multiply-accumulate unit
using an adaptive supply voltage and body bias architecture,” IEEE Journal of Solid-
State Circuits, vol. 37, pp. 1545–1554, Nov 2002.
[25] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De,
“Adaptive body bias for reducing impacts of die-to-die and within-die parameter
variations on microprocessor frequency and leakage,” IEEE Journal of Solid-State
Circuits, vol. 37, pp. 1396–1402, Nov 2002.
[26] S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, “Design of a Process Varia-
tion Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS,”
IEEE Journal of Solid-State Circuits, vol. 42, pp. 1370–1382, June 2007.
[27] T.-H. Kim, J. Liu, and C. Kim, “A Voltage Scalable 0.26 V, 64 kb 8T SRAM With
Vmin Lowering Techniques and Deep Sleep Mode,” IEEE Journal of Solid-State
Circuits, vol. 44, pp. 1785–1795, June 2009.
[28] J. Kulkarni, K. Kim, and K. Roy, “A 160 mV Robust Schmitt Trigger Based Sub-
threshold SRAM,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 2303–2313,
Oct. 2007.
[29] N. Verma and A. Chandrakasan, “A 256 kb 65 nm 8T Subthreshold SRAM Employ-
ing Sense-Amplifier Redundancy,” IEEE Journal of Solid-State Circuits, vol. 43,
pp. 141–149, Jan. 2008.
[30] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using
a minimum energy design methodology,” IEEE Journal of Solid-State Circuits,
vol. 40, pp. 310–319, Jan. 2005.
[31] J. Chen, L. Clark, and T.-H. Chen, “An Ultra-Low-Power Memory With a Sub-
threshold Power Supply Voltage,” IEEE Journal of Solid-State Circuits, vol. 41,
pp. 2344–2353, Oct. 2006.
[32] T.-H. Kim, J. Liu, J. Keane, and C. Kim, “A High-Density Subthreshold SRAM
with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme,” in
IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 330–606,
Feb. 2007.
[33] K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, “A bitline leakage compensation
scheme for low-voltage SRAMs,” IEEE Journal of Solid-State Circuits, vol. 36,
pp. 726–734, May 2001.
[34] B. Calhoun and A. Chandrakasan, “Ultra-dynamic Voltage scaling (UDVS) using
sub-threshold operation and local Voltage dithering,” IEEE Journal of Solid-State
Circuits, vol. 41, pp. 238–245, Jan. 2006.
[35] B. Calhoun and A. Chandrakasan, “Static noise margin variation for sub-threshold
SRAM in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 1673–
1679, July 2006.
[36] B. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and sizing for minimum
energy operation in subthreshold circuits,” IEEE Journal of Solid-State Circuits,
vol. 40, pp. 1778–1786, Sept. 2005.
[37] M.-T. Chang and W. Hwang, “A fully-differential subthreshold SRAM cell with
auto-compensation,” in IEEE Asia Pacific Conference on Circuits and Systems,
pp. 1771–1774, Dec. 2008.
[38] R. Gonzalez, B. Gordon, and M. Horowitz, “Supply and threshold voltage scaling
for low power CMOS,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 1210–
1216, Aug 1997.
[39] K. Kanda, H. Sadaaki, and T. Sakurai, “90sense-amplifying memory cell,” IEEE
Journal of Solid-State Circuits, vol. 39, pp. 927–933, June 2004.
[40] T.-H. Kim, J. Liu, and C. Kim, “An 8T Subthreshold SRAM Cell Utilizing Reverse
Short Channel Effect for Write Margin and Read Performance Improvement,” in
IEEE Custom Integrated Circuits Conference, pp. 241–244, Sept. 2007.
[41] Y.-C. Lai and S.-Y. Huang, “X-Calibration: A Technique for Combating Excessive
Bitline Leakage Current in Nanometer SRAM Designs,” IEEE Journal of Solid-State
Circuits, vol. 43, pp. 1964–1971, Sept. 2008.
[42] K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura,
N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, and H. Shinohara, “A 45-nm
single-port and dual-port SRAM family with robust read/write stabilizing circuitry
under DVFS environment,” in IEEE Symposium on VLSI Circuits Dig. Tech. Papers,
pp. 212–213, June 2008.
[43] K. Osada, H. Higuchi, K. Ishibashi, N. Hashimoto, and K. Shiozawa, “A 2 ns ac-
cess, 285 MHz, two-port cache macro using double global bit-line pairs,” in IEEE
International Solid-State Circuits Conference Dig. Tech. Papers, pp. 402–403, 494,
Feb 1997.
[44] J. Rabaey, Low Power Design Essentials. Springer Publishing Company, Incorpo-
rated, 2009.
[45] K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, R. Uchida, Y. Nakazawa, Y. Hi-
rota, S. Yoshida, and T. Saito, “Per-bit sense amplifier scheme for 1GHz SRAM
macro in sub-100nm CMOS technology,” in IEEE International Solid-State Circuits
Conference Dig. Tech. Papers, pp. 502–542, Feb. 2004.
[46] J. Wang, S. Nalam, and B. H. Calhoun, “Analyzing static and dynamic write margin
for nanometer SRAMs,” in Proceeding of International Symposium on Low Power
Electronics and Design, pp. 129–134, August 2008.
[47] B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, “A Sub-200mV 6T SRAM in
0.13mm CMOS,” in IEEE International Solid-State Circuits Conference Dig. Tech.
Papers, pp. 332–606, Feb. 2007.
[48] B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, “A Variation-Tolerant Sub-200 mV
6-T Subthreshold SRAM,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 2338–
2348, Oct. 2008.