在本篇論文中主要探討如何達成低電壓與高速度之浮動閘式(Floating-Gate)快閃記憶體(Flash Memory)。希望藉由有效降低穿隧氧化層(Tunneling Oxide)厚度或者矽閘間層(Inter-Poly Dielectric)的等效氧化層厚度(Effective Oxide Thickness)，來獲致較佳的浮動閘式快閃記憶體。其中，並探討金屬閘極與高介電常數矽閘間層應用於浮動閘式快閃記憶體之可行性。於整個研究中，先以二維元件模擬來分析各種元件設計參數下其記憶體的寫入及抹除性能。接著，再進行浮動閘式快閃記憶體的實驗實做，完成記憶體元件及電容元件，以驗證元件模擬之各種電性結果。最後，量測評估可靠度上的潛在風險。

The objectives of this thesis is to explore in depth the feasibility of low-voltage, high-speed Floating-Gate (FG) Flash memory cell through the proper minimizations of tunneling oxide and inter-poly dielectric (IPD) layers. Here, high-k materials and metal control gate are adopted in stacked gate to promote the control gate coupling ratio. Detailed investigations of device parameters in FG Flash cells are performed with two-dimensional device simulations and real silicon fabrications to attain the possible high-speed and low-power Flash cell design.

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