研究生: |
黃冠庭 Hanug, Kaung-Ting |
---|---|
論文名稱: |
高強度屏蔽奈米化矽基板之應力控制以抑制氮化鎵磊晶後基板翹曲 Stress control of high strength sealed nanotextured silicon wafer to resist warpage after GaN epitaxy |
指導教授: |
葉哲良
Yeh, J. Andrew |
口試委員: |
侯帝光
Hou, Max T. 林育芸 Lin, Yu-Yun 徐文慶 Hsu, Wen-Ching |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 奈米工程與微系統研究所 Institute of NanoEngineering and MicroSystems |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 中文 |
論文頁數: | 80 |
中文關鍵詞: | 矽基氮化鎵 、奈米化 、強度提升 、應力控制 、磊晶 |
外文關鍵詞: | GaN-on-Si, nanotexturing, strength enhancement, stress control, epitaxy |
相關次數: | 點閱:3 下載:0 |
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氮化鎵(GaN)為非常熱門且發展性極高的的半導體材料,目前大部分利用外延性磊晶生長(Epitaxy)製得,使磊晶用基板成為重要的研究對象,其中矽基板因技術獲得突破、加工技術成熟且成本相對低廉逐漸受到矚目成為磊晶用基板的趨勢,因其具有可大尺寸成長(large-scale growth) 及大規模生產(mass production) 的優點,使矽基板於多種磊晶片的選項中更具競爭力。但GaN on Si仍因為異質材料會衍生出許多問題,其中因材料熱不匹配所導致的氮化鎵磊晶過程中基板翹曲(warpage)程度的大量變化導致基板或氮化鎵薄膜破裂的問題 尤其嚴重。
本研究主要透過利用奈米結構分散應力的效果提升基板強度並控制保護層
應力,以克服氮化鎵磊晶時之應力,使目前業界常用於磊晶氮化鎵之6 吋矽基板的厚度1000 μm 減薄至一般積體電路製程機台承載的標準片厚度675 μm,同時磊晶後之氮化鎵特性預期維持與1000 μm 厚度基板相同,並於奈米結構上沉積由二氧化矽、非晶矽薄膜構成之保護層,並控制此保護層應力,使此保護層除了能達到屏蔽奈米結構的效果,更能降低氮化鎵磊晶後基板翹曲,使後續製成能順利進行,另外透過deep-RIE改善奈米結構製備或改變保護層材料為氮化矽,解決新型基板側邊容易產生回融蝕刻的問題。本實驗之最終目標為研發高強度之氮化鎵磊晶用矽基板,基板製備完成後磊晶3.4 μm 氮化鎵並於其上製作簡易電晶體,後續實驗將與市售之一般675 μm 及1000 μm 氮化鎵磊晶片比較,對新型基板之強度提升效果及應用可行性。
Gallium nitride (GaN) is a very great and growth-oriented semiconductor material in recent years, which is mostly growth by epitaxy in industry. It makes the substrate for epitaxy GaN become a big issue. Among different kinds of substrates, Silicon is very competitive because of the breakthrough technology, mature fabrication technique and low cost, and also because Si substrate processes the advantages of large scale growth and mass production. But GaN-on-Si still derives many problems because of Heterogeneous materials. The most serious problem is the large amount of warping change in the GaN epitaxy process, it will cause the crack of Si substrate or GaN thin film.
This research is mainly focus on enhancing the strength of Si substrate by the stress distribution effect of nanostructure and control the stress of the protecting layer, to overcome the stress induced by GaN epitaxy.We fabricate nanostructure on Si wafer to thinner the thickness of 6 inch Si wafer used for epitaxy GaN from 1000 μm to 675μm, which is the compliant thickness industry using, and the GaN film properties on nanotextured substrate are expected to be the same with which on 1000 μm substrate. Furthermore deposit the covering layer composed of silicon dioxide and amorphous-silicon on nanostructure and control the stress of the covering layer. Therefore, the covering layer achieve the desired effects to protect nanostructure from destroyed and to reduce the warping condition after GaN epitaxy.
The ultimate goal of this research is to create a high strength GaN-on-Si substrate. After preparation of the substrate, epitaxy 3μm thin film and then fabrication simple transistor on the thin film. Finally, verifies its feasibility by comparing the properties of GaN and transistor with normal 1000 μm and 675 μm substrates.
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