近年來由於行動電子產品的蓬勃發展使得非揮發性快閃記憶體快速成長，然而未來的繼續微縮卻因目前頗高的操作電壓而充滿著嚴峻的挑戰。本論文提出一個創新概念的蕭特基多位元電荷捕捉式快閃記憶體作為未來非揮發性記憶體的可行方案，利用二維模擬軟體展示其於寫入、抹除與讀取各操作方式之特性，並探究相應之物理機制，同時發展出載子注入機率之物理模型。
不同於傳統元件的行為，於蕭特基元件中，電子與電洞皆可經由穿隧蕭特基能障而進入通道。利用此雙向導通之特性，當施加正閘極電壓時，蕭特基快閃記憶體可利用特殊的源極端將高能電子注入方式進行寫入動作；同理，當施加負閘極電壓時便可以引起熱電洞於汲極端注入進行抹除動作。此獨特的寫入與抹除方式可以有效避免在一般元件中閘極與源極/汲極間的電壓衝突效應，達成低電壓與高效能之寫入抹除操作。
在讀取的動作上，多位元蕭特基快閃記憶體可利用電荷捕捉式記憶體之標準的雙向反轉讀取方式來進行。雖然蕭特基元件之雙向導通特性可能造成記憶體讀取上之可能誤判，但是經由元件參數及讀取動作之深入探討，蕭特基能障記憶體具備獨特的穩定性。而在微縮上，因為其特殊之電子注入寫入及電洞注入抹除行為，使其儲存載子之分布相對緊密與勻稱；更因蕭特基接面之獨特能障，於元件微縮時可有效抑制短通道效應，使其成為未來極具優勢之多位元記憶體之候選者。

[1] R. Bez, P. Cappelletti, G. Casagrande and A. Pirovano, Nonvolatile Memories: Novel Concepts and Emerging Technologies, Spring, 2008.
[2] International Technology Roadmap for Semiconductor, 2007 edition.
[3] Marvin H. White, Dennis A. Adams, and Jiankang Bu “On the go with SONOS” in ESSDRC, pp. 399□402, 2003.
[4] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells:—An overview", Proc. IEEE, vol. 85, pp. 1248 - 1271 , 1997.
[5] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory,” in Proc. IEEE, vol. 91, pp. 489 - 502, 2003.
[6] C.-G. Hwang, “Nanotechnology enables a new memory growth model,” in Proc. IEEE, vol. 91, no. 11, pp. 1765-1771, 2003.
[7] A. Fazio and M. Bauer, “Intel strataFlash™ memory development and implementation,” in J. Intel Technol., vol. Q4, 1997.
[8] G. Atwood, “Future Directions and Challenges for ETox Flash Memory Scaling,” IEEE Trans. Device and Materials Reliability, vol. 4, pp. 301-305, Sep. 2004.
[9] M. Bauer M. Bauer, R. Alexis, G.Atwood, B. Battar, A. Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, K. Wojciwhowski, “A multilevel-cell 32 Mb Flash memory,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1995, pp. 132–133.
[10]B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
[11]K. Kim, “Technology for sub 50nm DRAM and NAND Flash manufacturing,” in IEDM Tech. Dig., 2005, pp. 539-543.
[12] G. Molas, D. Deleruyelle, B. De Salvo, G. Ghibaudo, M. Gely, S. Jacob, D. Lafond and S. Deleonibus, “Impact of few electron phenomena on floating-gate memory reliability,” in IEDM Tech. Dig., 2004, pp. 877-880.
[13] S. Lai, "Flash memories: Where we were and where we are going", in IEDM Tech. Dig., pp. 971 - 973, 1998.
[14] S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masuoka, “Reliability Issues of Flash Memory Cells,” Proc. IEEE, vol. 81, pp. 776 - 788, 1993.
[15] P. Blomme, and J. V. Houdt, “Scalability of Fully Planar NAND Flash Memory Arrays below 45nm,”in IEEE Proc. IMW, 2009, pp. 1-2.
[16] A. Ghetti, C. Monzio Compagnoni, F. Biancardi, A. L. Lacaita, S. Beltrami, L. Chiavarone, A.S. Spinelli, and A. Visconti, “Scaling trends for random telegraph noise in deca-nanometer Flash memories,” in IEDM Tech. Dig., pp. 1 - 4, 2008.
[17] C. Monzio Compagnoni, R. Gusmeroli, A. S. Spinelli, Andrea L. Lacaita, M. Bonanomi, and A. Visconti, " Statistical Model for Random Telegraph Noise in Flash Memories," IEEE Trans. Electron Devices, Vol. 55, No. 1, pp. 388–395, Jan. 2008.
[18] M.H. White and D.C. Adams, "Low voltage SONOS nonvolatile semiconductor memories (NVSMs)," in Proc. 2000 COMAC, Anaheim, CA, pp. 383.
[19] M. K. Cho and D. K. Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: Compatibility issue with current Flash technology,” IEEE Electron Device Lett., vol. 21, pp. 399–401, Sep. 2000.
[20] Chimoon Huang, Tahui Wang, T. Chen, N. C. Peng, A. Chang, and F. C. Shone, “Characterization and simulation of hot carrier effect on erasing gate current in flash EEPROM’s,” in Proc. IRPS, 1995, pp. 61–64.
[21] E. J. Prinz, G. L. Chindalore, K. Harber, C. M. Hong, C. B. Li, and C. T. Swift, “An embedded 90 nm SONOS Flash EEPROM utilizing hot electron injection programming and 2-sided hot hole injection erase,” in Proc. IEEE NVSMW, 2003, pp. 56–57.
[22] Kirk Prall, “Scaling Non-Volatile Memory Below 30nm,” in Proc. IEEE NVSMW, 2007, pp. 5–10.
[23] A. Datta, P. Bharath Kumar, and S. Mahapatra, “Dual-Bit/Cell SONOS Flash EEPROMs: impact of channel engineering on programming speed and bit coupling effect,” IEEE Electron Device Lett., vol. 28, pp. 446–448, May 2007.
[24] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Electrons retention model for localized charge in oxide–nitride–oxide (ONO) dielectric,” IEEE Electron Device Lett., vol. 23, pp. 556–558, Sep. 2003.
[25] K. Kim, and J. Choi, “Future Outlook of NAND Flash Technology for 40nm Node and Beyond,” in 21st NVSNW, pp. 6□10, Feb. 2006.
[26] M. P. Lepselter, and S. M. Sze, “SBIGFET: An Insnlated-Gate Field-Effect Transistor Using Schottky Barrier Contacts fer Source and Drain,” in Proc. IEEE, vol. 56, no. 8, pp. 1400-1402, 1968.
[27] C. J. Koeneke, S.M. Sze, R.M. Levin, and E. Kinsbron, “Schottky MOSET in VLSI,” in IEDM Tech. Dig., pp. 367-370, 1981.
[28] Chung-Kuang Huang, Wei E. Zhang, and C. H. Yang, “Two-Dimensional Numerical Simulation of Schottky Barrier MOSFET with Channel Length to 10 nm,” IEEE Trans. Electron Devices, Vol. ED-45, No. 4, pp. 842–848, Apr. 1998.
[29] M. Ieong, Paul M. Solomon, S.E. Laux, Hon-Sum Philip Wong, and D. Chidambarrao “Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model,”in IEDM Tech. Dig., pp. 733-736, 1998.
[30] Chun-Hsing Shih, San-Pin Yeh, Ji-Ting Liang, and Yan-Xiang Luo, “Source-side injection Schottky barrier Flash memory cells,” Semiconductor Science and Technology, Vol. 24, 025013, Feb. 2009.
[31] S.-J. Choi, J.-W. Han, S. Kim, D.-H. Kim, M.-G. Jang, J.-H. Yang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song,, Y. C. Park, J. W. Kim, and Y.-K. Choi, “High Speed Flash Memory and 1T-DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS Device for Multi-functional SoC Applications,” in IEDM Tech. Dig., 2008, pp. 1-4.
[32] S.-J. Choi, J.-W. Han, S. Kim, M.-G. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “Enhancement of Program Speed in Dopant-Segregated Schottky-Barrier (DSSB) FinFET SONOS for NAND-Type Flash Memory,” IEEE Electron Device Lett., vol. 30, pp. 78–81, Jan. 2009.
[33] S.-J. Choi, J.-W. Han, M.-G. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for NOR-type Flash Memory,” IEEE Electron Device Lett., vol. 30, pp. 265–268, Mar. 2009.
[34] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D Schottky barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, pp. 1048-1058, May 2006.
[35] M. Nishisaka, S. Matsumoto, and T. Asano, “Schottky source/drain SOI MOSFET with shallow doped extension,” Jpn. J. Appl. Phys., part 1, vol. 42, pp. 2009-2013, Apr. 2003.
[36] L. Selmi, E. Sangiorgi, R. Bez, and B. Riccb, “Measurement of the hot hole injection probability from Si into SiO2 in p-MOSFETs,” in IEDM Tech. Dig., 1993, pp. 333-336.
[37] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Electrons retention model for localized charge in oxide–nitride–oxide (ONO) dielectric,” IEEE Electron Device Lett., vol. 23, pp. 556–558, Sep. 2003.
[38] J.A. Kittl, W.T. Shiau, Q.Z. Hong, and D. Miles, “Salicides: materials, scaling and manufacturability issues for future integrated circuits,” Microelectronic Engineering, vol. 50, no. 1-4, pp. 87-101, Jan. 2000.
[39] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D Schottky barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, pp. 1048-1058, May 2006.
[40] Hiroshi Iwai, Tatsuya Ohguro, and Shun-ichiro Ohmi, “NiSi salicide technology for scaled CMOS,” Microelectronic Engineering, vol. 60, no. 1-2, pp. 157-169, Jan. 2002.
[41] Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, 2006.
[42] K. Matsuzawa, K. Uchida and A. Nishiyama, “A unified simulation of Schottky and Ohmic contacts,” IEEE Trans. Electron Devices, vol. 47, pp. 103-108, Jan. 2000.
[43] J. M. Andrews and M. P. Lepselter, “Reverse current-voltage characteristics of metal-silicide Schottky diodes,” Solid-State Electronics, vol. 13, pp. 1011-1023, 1970.
[44] S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain,” IEEE Trans. Electron Devices, vol. 52, pp. 1859-1867, Aug. 2005.
[45] J. M. Andrews and M. P. Lepselter, “Reverse current-voltage characteristics of metal-silicide Schottky diodes,” Solid-State Electronics, vol. 13, pp. 1011–1023, 1970.
[46] S. Tam, P.-K. Ko and C. Hu, “Lucky-electron model of channel hot electron injection in MOSFET’s,” IEEE Trans. Electron Devices, vol. 31, pp. 1116–1125, Sep. 1984.
[47] Y. Igura, H. Matsuoka and E. Takeda “New device degradation due to "cold" carriers created by band-to-band tunneling,” IEEE Electron Devices Lett., vol. 10, pp. 227-229, May. 1989.
[48] K. K. Young, “Short-channel effect in fully depleted SOI MOSFET’s,” IEEE Trans. on Electron Devices, Vol. 36, No. 2, pp. 399–402, Feb. 1989.
[49] M. Nishisaka, S. Matsumoto, and T. Asano, “Schottky source/drain SOI MOSFET with shallow doped extension,” Jpn. J. Appl. Phys., part 1, vol. 42, pp. 2009-2013, Apr. 2003.
[50] S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain,” IEEE Trans. Electron Devices, vol. 52, pp. 1859-1867, Aug. 2005.
[51] Chun-Hsing Shih and San-Pin Yeh, “Device considerations and design optimizations of dopant segregated Schottky barrier MOSFETs,” Semiconductor Science and Technology, vol. 23, 125033(10pp), Dec. 2008.
[52] S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain,” IEEE Trans. Electron Devices, vol. 52, pp. 1859-1867, Aug. 2005.
[53] Zhen Zhang, Zhijun Qiu, Ran Liu, Mikael Östling, and Shi-Li Zhang, "Schottky-barrier height tuning by means of ion implantation into preformed Silicide films followed by drive-in anneal, " IEEE Electron Device Lett., Vol. 28, pp. 565-568, July 2007.
[54] Mantavya Sinha, Eng Fong Chor, and Yee-Chia Yeo, "Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation," Appl. Phys. Lett., vol. 76, pp. 3992-3994, Jun. 2000.
[55] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique” in Symp. VLSI, pp. 168-169, 2004.
[56] Mantavya Sinha, Rinus Tek Po Lee, Eng Fong Chor, and Yee-Chia Yeo, “Schottky barrier height modulation of Nickel–Dysprosium-Alloy Germanosilicide contacts for strained P-FinFETs” IEEE Electron Device Lett., Vol. 30, pp. 1278-1280, 2009.
[57] Emre Alptekin and Mehmet C. Ozturk, “Tuning of the Nickel Silicide Schottky Barrier height on p-Type silicon by Indium implantation,” IEEE Electron Device Lett., Vol. 30, pp. 1272-1274, 2009.
[58] A. Bansal, B. C. Paul, and K. Roy, “An analytical fringe capacitance model for interconnects using conformal mapping” IEEE Trans. Computer-Aided Design, vol. 25, pp. 2765–2774, Dec. 2006.
[59] K. Hasnat, C.-F. Yeap, S. Jallepalli, W.-K. Shih, S. A. Hareland, V. M. Agostinelli, Jr., A. F. Tasch, Jr., and C. M. Maziar, “A Pseudo-Lucky Electron Model for Simulation of Electron Gate Current in Submicron NMOSFET’s, ” IEEE Trans. Electron Devices, vol. 43, pp. 1264–1273, Aug. 1996.
[60] Y. Taur and Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, 2nd edition, 2009.
[61] A. Bansal, B. C. Paul, and K. Roy, “An analytical fringe capacitance model for interconnects using conformal mapping” IEEE Trans. Computer-Aided Design, vol. 25, pp. 2765–2774, Dec. 2006.