全系統模擬對於Embedded System設計驗證至關重要。其Flexibility與Early Availability性質特別適合設計初期探索與驗證系統行為。然而,傳統的模擬加速方法通常會遭遇Performance、Accuracy或是Scalability之困難。因此,本計畫提出VIRA (VIRtualization-Assisted)方法,建立Fast、Accurate與Scalable之全系統模擬器以克服上述困難。為了增加模擬效能,VIRA將Hardware-Assisted Component執行於Host HardwareDevice以得到Native Execution之效能。為了確保Accuracy與正確的Data Dependency,本計畫提出了一個包含Bus Contention Delay之Deterministic Timing Model。為了增加擴充功能,VIRA整合了Software-Modeled Component以支援新增功能,並使用快速Data Pass-Through機制以減少被模擬元件間的Communication Overhead。我們透過在市售的SoC(System-on-Chip)板上實作此一技術來驗證所提出的Virtualization-Assisted全系統模擬。實驗結果顯示,除了能夠得到正確的Inter-Component Interaction結果,執行速度也比Commercial Functional Simulator快了58〜625倍。

We propose in this thesis a near-real-time performance full-system simulation approach with hardware acceleration using virtualization techniques. Traditional acceleration approaches generally cannot capture inter-component interactions due to unpredictable component simulation progress. Our approach leverages existing hardware virtualization framework and devises three key implementation techniques to achieve fast and accurate full-system simulations. First, our approach utilizes the virtualization framework trap mechanism and precisely intercepts inter-component interactions with no need to check every data access, but effectively maintains deterministic chronological orders of inter-component interactions. Second, VIRA provides very accurate system performance estimation for early system-level designs through effective integration of component timing models, interrupt effects, and bus contention analysis. Third, VIRA achieves near-real-time performance by having software and hardware simulated components executed on the same host machine to minimize the overhead of inter-component data exchange. We implement the proposed approach on a virtualization-enabled off-the-shelf System-on-Chip board to demonstrate the effectiveness of our idea. The experiments show that VIRA always produces deterministic results while running 58~625 times faster than a commercial tool and the system performance estimation is only 3~6% from real systems. Moreover, our deterministic full-system simulator is also verified to carry as little as 2~57% overhead compared to ideal native executions on the same host hardware devices.

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