功率消耗已經成為了滿足摩爾定律上的一個主要的瓶頸。為了解決這樣的議題，近期許多低功耗的前瞻技術陸續被研究探索。於設計層級面來說，傳統上我們期待電路設計是能夠在不發生任何錯誤下運作的，然而，對於錯誤可容忍(error resilient)的應用來說，例如：影像處理，百分之百的正確性卻不是必須的。藉由將正確性的目標訂在小於百分之百，則對應的功率消耗將可以大幅地被降低。最近，機率性的互補式金屬氧化物場效電晶體(Probabilistic CMOS, PCMOS)以及機率性布林電路(Probabilistic Boolean Circuits, PBCs)已經被提出來以處理功率消耗的議題。

另一方面，於元件層級面，單電子電晶體(Single-Electron Transistor, SET)因為其於室溫下的超低功耗表現，已經被視為一種有潛力的元件以延續摩爾定律。而且，一個可重構的單電子電晶體陣列(reconfigurable SET array)的架構也已經被提出來以解決可靠性的問題。最近，許多自動化映射(mapping)合成的方法也相繼地被提出來以優化可重構單電子電晶體陣列的面積。

然而，這兩項技術的自動化流程仍然不夠完善。對於機率性布林電路的技術，目前尚未提出正確性(correctness)分析的方法以及功率最佳化的演算法。而對於單電子電晶體的技術來說，目前被提出的映射方法中並沒有考慮到陣列中的元件奈米線發生缺陷的情形。還有，當進行缺陷可察覺的映射(defect-aware mapping)之前，單電子電晶體陣列中發生缺陷的位置也是要事先診斷出來的。因此，在此篇論文中，我們將針對上述的議題提出對應的解決方案。

對於機率性布林電路的部分，我們首先提出一個統計方法以評估機率性布林電路的正確性。接著，我們對於機率性布林電路提出數個功率最佳化的策略。最後，我們把提出的最佳化策略和正確性分析整合成一套功率最佳化的演算法。實驗結果顯示我們提出的正確性分析方法具有很高的效率以及準確率，且我們提出的功率最佳化演算法在一組IWLS 2005的測試資料上，當正確性設定為90%時，平均可以省下36%的功率-延遲-乘積(power-delay-product)。

對於單電子電晶體陣列的部分，此篇論文第一個提出了診斷方法以辨別出單電子電晶體陣列中缺陷的位置，隨後並對於不同的情況提出兩種考慮到缺陷位置之映射方法。實驗結果顯示我們所提出的診斷方法可以在假設的缺陷率和缺陷分佈下找出所有的缺陷。且我們所提出的映射方法也可以成功地映射出對應功能的單電子電晶體陣列，平均來說，在5000 ppm的缺陷率下，基本繞路映射演算法(baseline detour mapping algorithm)以及缺陷再利用映射演算法(defect-reuse mapping algorithm)對於陣列寬度上的額外增加分別為11.13%以及7.69%。

Power consumption has become one of the primary bottlenecks to meet the Moore's law. To deal with this issue, many emerging low power technologies have been explored recently. At the design level, traditionally, we expect that circuit designs can be executed without errors. However, for error resilient applications such as image processing, 100% correctness is not necessary. By pursuing less than 100% correctness, power consumption can be significantly reduced. Recently, Probabilistic CMOS (PCMOS) and Probabilistic Boolean Circuits (PBCs) have been proposed to deal with power consumption issue.

On the other hand, at the device level, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. Furthermore, a reconfigurable SET array architecture has been proposed to deal with the reliability issue. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays.

However, the automation flows for these two technologies are still not robust. For the PBC technology, no correctness analysis and power optimization algorithms were proposed. As for the SET array technology, no mapping algorithms considering the existence of defective nanowire segments were proposed. Furthermore, before the defect-aware mapping, we have to know the locations of defects in SET arrays. Therefore, in this dissertation, we propose corresponding solutions to deal with these issues.

For the part of PBC, we first propose a statistical approach for evaluating the correctness of PBCs. Then, we propose strategies for power optimization of PBCs. Finally, we integrate these strategies with the correctness analysis as a power optimization algorithm for PBCs. The experimental results show that the proposed correctness analysis method is highly efficient and accurate, and that the power optimization algorithm saves 36% of total power-delay-product on average under a correctness constraint of 90% on a set of IWLS 2005 benchmarks.

For the part of SET array, this dissertation presents the first diagnosis approach to identify the locations of defects in SET arrays followed by two defect-aware algorithms for mapping SET arrays in different scenarios. The experimental results show that the proposed diagnosis method can detect 100% of defects under a defect rate and distribution in SET arrays. As for the mapping algorithms, the results show that our approach can successfully map the SET arrays with 11.13% and 7.69% width overhead on average in the baseline detour mapping algorithm and defect-reuse mapping algorithm, respectively, in the presence of 5000 ppm defects.

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