非揮發性隨機存取記憶體之測試及良率提升方法

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研究生：	陳靜怡 Chen, Ching-Yi
論文名稱：	非揮發性隨機存取記憶體之測試及良率提升方法 Testing and Yield Enhancement Methods for Nonvolatile Random Access Memories
指導教授：	吳誠文 Wu, Cheng-Wen
口試委員:	張孟凡黃稚存黃錫瑜呂學坤李進福陳竹一
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	101
語文別：	英文
論文頁數：	116
中文關鍵詞：	記憶體測試、非揮發性記憶體、磁性隨機存取記憶體、電阻式隨機存取記憶體、錯誤模型、故障分析、寫入干擾錯誤、讀取干擾錯誤、過度初始化、良率
外文關鍵詞：	Memory testing, Nonvolatile memory (NVM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), fault model, failure analysis, write disturb fault, read-one disturb fault, over-forming, yield
相關次數：	點閱：3 下載：0
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磁性隨機存取記憶體(Magnetic Random Access Memory, MRAM)以及電阻式隨機存取記憶體(Resistive Random Access Memory, RRAM)是新型的非揮發性記憶體，相較於目前時興的快閃記憶體(Flash Memory)，這些新型的記憶體有存取速度快、耐用時間長、相容於邏輯製程等優點，未來很有可能被廣泛應用於系統單晶片(System-On-Chip)及記憶體系統中。目前電阻式隨機存取記憶體尚在研發階段，磁性隨機存取記憶體當中的翻轉式磁性隨機存取記憶體(Toggle MRAM)則在近幾年進入量產；然而此兩種記憶體皆尚未有完整之測試相關技術。在記憶體開發過程中，面對未成熟的技術、製程變異造成之缺陷問題、以及進入市場時程壓力等挑戰，為了確保產品的品質及良率，記憶體設計必須同時涵蓋診斷及測試等相關技術的開發。本論文中，我們針對翻轉磁性隨機存取記憶體及電阻式隨機存取記憶體分別提出了測試演算法、良率提升方法、以及相關之電路設計。
反轉式磁性隨機存取記憶體因為製程變異造成的操作區間漂移問題，可能會發生寫入干擾錯誤(Write Disturbance Fault)，然而記憶體常用的行進式測試(March test)卻只能涵蓋部分的寫入干擾錯誤。為提高寫入干擾錯誤之涵蓋率(Fault coverage)以確保產品品質，我們提出了測試演算法March RP，其能涵蓋大部分寫入干擾錯誤；量測結果亦顯示此測試法有較高的錯誤偵測能力。此外，針對操作區間漂移造成的反轉式磁性隨機存取記憶體良率下降問題，我們也提出了一個內建自我設定操作電流(Built-In Self-Configure)電路架構，其能利用提出的螺旋搜尋演算法(Spiral Search)迅速找出適當的操作點，並將記憶體設定在此操作電流上以提升記憶體良率。模擬結果顯示，相較於傳統的記憶體特性測試(Characterization test)，此電路能以更低的測試成本卻更迅速地為操作點漂移之問題晶片重新找到適當的操作電流。
電阻式隨機存取記憶體是近幾年開發出的新型記憶體，過去的研究主要為各種元件材料及特性的分析，目前有部分種類如氧化鉿(HfO2-based)式的電阻式元件表現出較佳潛力、並已進入電路原型開發階段，可能很快會進入非揮發性記憶體產品之競爭行列。目前電路原型之開發尚面臨良率問題，然而卻尚未有任何測試相關之技術發表。我們首先針對氧化鉿電阻式記憶體提出了初始化過度缺陷(Over-Forming defect)及讀一干擾(Read-One-Disturb)錯誤，並提出了能涵蓋傳統隨機存取記憶體錯誤種類以及此兩項缺陷及錯誤模型之測試演算法March C*。以此測試演算法量測晶片之結果，證明了讀一干擾錯誤之行為確實存在於電阻式記憶體中。我們也提出了一種初始化方法及內建式自我初始化(Built-In Self-Forming)電路設計，晶片之量測結果顯示此初始化方法相較於傳統使用機台之初始化程序，能在非常短的時間內達到非常高的初始化效果。
部分的非揮發性記憶體其耐用時間有限，老化的記憶體位元會隨使用時間增加，若一筆資料中的錯誤位元超過了錯誤更正(Error detection and correction)電路之修正能力，系統將會發生操作錯誤。本論文針對隨機存取記憶體提出了一個基於蕭氏碼(Hsiao Code)之可變碼率(Adaptive code rate)錯誤更正電路架構，當故障之記憶體位元增加，即可切換錯誤更正電路至碼率較低、修復能力較高之編解碼模式，藉此延長記憶體的使用時間。模擬結果顯示，在同樣的可靠度(Reliability)要求下，相較於傳統的錯誤更正電路，本文所提出之可變碼率錯誤更正電路能容忍較多的錯誤位元發生。

This thesis presents the test and yield enhancement associated works for the emerging nonvolatile random access memories (RAMs), specifically the Magnetic Random Access Memory (MRAM) and Resistive Random Access Memory (RRAM).
We first address MRAM, which is an emerging nonvolatile memory widely studied for its high speed, high density, and almost unlimited endurance. However, for deep-submicron process technologies, significant variation in MRAM cells’ operating condition results in write failures in cells and reduces the production yield. The Write Disturbance Fault (WDF) due to the operating region shift is a fault model specific to toggle MRAM. March tests have high coverage for conventional RAM faults; however, they do not cover all WDFs. To improve quality of MRAM products, we propose a new test algorithm. The test result of fabricated chips shows the proposed algorithm has higher WDF coverage than traditional March tests. A 1-Mb MRAM prototype chip with the proposed built-in self-test (BIST) circuit has been designed and fabricated using a 0.15m CMOS technology.
In addition to test method, we also present a built-in self-configure (BISC) scheme for toggle MRAM to improve the chip yield that may reduce due to variation in the chip’s operating region. The BISC circuit uses a search method to efficiently find and configure each individual chip a suitable operating current through few tester channels. The simulation result shows that the BISC finds the suitable operating point for failed chips in much less time compared with the conventional ATE approach. Production yield thus can be increased while the test cost is greatly reduced.
We also discuss RRAM in detail, which is a new type of nonvolatile memory based on the resistive memory device. Over the past decade, many resistive memory devices have been investigated, and some promising ones are identified. Research groups are currently moving from the resistive device development stage to the memory circuit design and implementation stage, hoping to fabricate memory chips that can be deployed in the market in the near future. However, so far the low manufacturing yield is still a major issue for RRAM chips, which will benefit from the introduction of advanced testing methods. In the thesis, we define the Over-Forming (OF) defect and the Read-One-Disturb (R1D) fault specific to RRAM, and then propose a test algorithm to cover these defects and faults in addition to the conventional RAM faults. We also propose a training-based forming method and the built-in self-forming (BISF) circuit. The measurement result shows that the forming method significantly improves the bit yield in much less time than the conventional ATE-based high voltage forming procedure. The proposed test algorithm is applied to a 4-Mb HfO2-based RRAM test chip, and the measurement results show that OF defects and R1D faults do exist in the RRAM chip. We develop a novel squeeze-search scheme to identify the cell resistance. By identifying specific failure patterns and collecting resistance distribution of faulty cells, defects and faults are identified. By our diagnosis method, designers and process engineers will be able to improve the RRAM yield in a more cost-effective way.
In addition to the test and diagnosis methodologies, we also present a novel error detection and correction (EDAC) design for RAM. Certain types of NVM have limited endurance, in which the worn cells increase over time in field use. As the number of errors in a data word exceeds the correction capability of the EDAC, operation failure occurs. To extend the lifetime of nonvolatile RAM, we propose an adaptive code rate EDAC scheme. As the defective bits in the memory increases, the codec can be changed to a mode that provides higher correction capability and uses part of user storage for more parity bits, such that the lifetime of the memory is extended. Given a certain reliability level, the proposed design allows more error bits than a conventional EDAC design.

List of Figures .......................................................................................................................... vi
List of Tables ............................................................................................................................ ix
Chapter 1 Introduction ......................................................................................................... 1
1 Memory Testing, Diagnosis, and Failure Analysis ...................................................... 1
2 MRAM Testing and Yield Enhancement Method ....................................................... 4
3 Challenges in RRAM Testing ...................................................................................... 6
4 EDAC for Extending RAM Lifetime ........................................................................... 8
Chapter 2 Toggle MRAM and Write Disturbance Fault ................................................. 11
1 Toggle MRAM ........................................................................................................... 11
2 Operating Region Shift and the Write Disturbance Fault .......................................... 13
3 Yield Loss Due to Write Current Mismatch .............................................................. 21
Chapter 3 MRAM WDF Testing and Current Self-Configuration for Improving
Yield ............................................................................................................................. 23
1 New Test Method for WDF ........................................................................................ 23
1.1 Target WDF List ............................................................................................... 23
1.2 New Test Operation for WDF ........................................................................... 24
1.3 March RP Algorithm for MRAM Testing ........................................................ 27
1.4 Improved MRAM Diagnosis Algorithm ........................................................... 29
2 MRAM Built-In Self-Test Design .............................................................................. 29
iv
3 Built-In Write Current Self-Configure Scheme ......................................................... 31
3.1 Target Pass Rate ................................................................................................ 33
3.2 Spiral Search ..................................................................................................... 33
3.3 Early-Stop Mechanism ...................................................................................... 40
3.4 Discussions ....................................................................................................... 41
4 Experimental Results .................................................................................................. 43
4.1 Test Efficiency Comparison.............................................................................. 43
4.2 Current Search Time Evaluation ....................................................................... 46
Chapter 4 Resistive Random Access Memory .................................................................. 56
1 HfO2-Based RRAM Cell ............................................................................................ 56
2 RRAM Array Architecture ......................................................................................... 59
Chapter 5 RRAM Testing and Failure Analysis .............................................................. 61
1 The Over-Forming Defect .......................................................................................... 62
2 A Training-Based Forming Method ........................................................................... 62
3 Read-One Disturb Fault and Its Test Algorithm ........................................................ 64
4 Experimental Results .................................................................................................. 70
4.1 Squeeze-Search Scheme for Resistance Search ................................................ 70
4.2 Forming Efficiency Comparison ....................................................................... 71
4.3 Chip Measurement Result and Failure Analysis ............................................... 74
Chapter 6 Adaptive Code Rate EDAC for RAM ............................................................. 85
1 Hsiao Code Construction ............................................................................................ 85
2 Adaptive Code Rate EDAC Scheme .......................................................................... 86
3 EDAC Circuit and Generator Matrix Design ............................................................. 90
3.1 EDAC Architecture ........................................................................................... 90
3.2 Hardware Sharing ............................................................................................. 93
3.3 Fast Decision for Enabling the Parity Corrector ............................................... 96
v
4 Reliability Evaluation and Synthesis Result .............................................................. 98
Chapter 7 Conclusions and Future Work ....................................................................... 101
1 Conclusions .............................................................................................................. 101
2 Future Work ............................................................................................................. 103
2.1 MRAM Testing Methods for Process Variation ............................................. 103
2.2 Fault Modeling and the BISF Improvement for RRAM ................................. 105
2.3 EDAC Capability Enhancement in Nonvolatile RAMs .................................. 106
Bibliography .......................................................................................................................... 107
                                

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