In modern FPGAs, I/O blocks are organized into several I/O banks. It is disallowed for I/O objects of different voltage levels to be placed in the same I/O bank. An integer linear programming (ILP)-based method has been proposed in [6] and [7] to solve the I/O placement problem for FPGAs with multiple I/O standards. However, the previous works assumed an FPGA organization where all I/O locations are identical and did not consider many restrictions found in industrial FPGAs. This thesis follows and complements [6] and [7] by considering the restrictions on an industrial FPGA, Altera Stratix device. The following I/O placement restrictions on Stratix device are considered. (1) Each voltage-referenced pin in an I/O bank can only support a limited number of I/O objects. (2) I/O objects must be placed a certain pin distance away from a differential pair. (3) Not all I/O standards are supported by every I/O bank. (4) Some I/O banks share the same voltage-referenced pin. (5) Some I/O standards can accept more than one voltage level.

The restrictions stated above are modeled as ILP conditions and are added to the ILP formulation, and the experimental results are compared with an industrial CAD tool, Altera Quartus II. The experimental results show that the ILP-based approach is efficient and outperforms the Quartus II by a large margin in both the number of solved test cases and running time. The ILP-based approach solved 289 test cases among 300 test cases with an average running time of
7 seconds while Quartus II only solved 178 test cases with an average running time of 87 seconds.

[1] http://www.altera.com
[2] Altera Corp., “Stratix Device Handbook”, Product Data Sheet, Jan 2005.
[3] Altera Corp., “Stratix II Device Handbook”, Product Data Sheet, Mar 2005.
[4] J. Anderson, J. Saunders, S. Nag, C. Madabhushi, and R. Jayaraman, “A Placement Algorithm for
FPGA Designs with Multiple I/O Standards”, in Proc. of Int’l Conf. on Field-Programmable Logic
and Applications, Lecture Notes in Computer Science 1896 (R.W. Hartenstein and H. Gr ¨ unbacher,
eds.), pp. 211-220, Springer-Verlag, Berlin, 2000.
[5] M. Berkelaar, K. Eikland, P. Notebaert, lp solve, available from
http://groups.yahoo.com.tw/group/lp solve.
[6] W.K. Mak, “I/O Placement for FPGAs with Multiple I/O Standards”, in Proc. of ACM Int’l Symp. on
Field-Programmable Gate Arrays, pp. 51-57, Feb. 2003.
[7] W.K. Mak, “Modern FPGA Constrained Placement”, in Proc. of IEEE/ACM ASP-DAC, pp. 779-784,
Jan. 2005.
[8] http://www.xilinx.com
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