本篇論文將研究面積與基板電阻值對元件特性的影響，並且提出一套演算法，可將大面積元件電流密度與電壓關係圖(J-V)轉換成小面積元件J-V，有效排除基板電阻對大面積元件所造成的影響。
首先利用演算法從實際長型大面積元件J-V曲線導出同樣狀況下小面積元件的J-V曲線，並與實際值做比較，結果與實際相符，證明了此演算法的可行性；並從各種不同大面積尺寸的電池出發，透過此演算法多次後每一個得到的小面積電池J-V特性也吻合，也就是說這些不同尺寸的大面積電池都排除了基板電阻的影響，得到了一個不考慮基板電阻的J-V曲線。
接著就可利用此演算法比較並探討元件特性和內部電路參數隨著元件長度的變化趨勢，發現因為基板電壓降的問題使得元件長度增加，PCE、Jsc、FF都會下降，Voc則沒此問題所以不變；最後也會去比較並探討各種不同基板電阻和不同短路電流對元件特性的影響，發現隨著基板片電阻和短路電流的增加，元件微縮後各參數的變化百分比也會變大，而由各參數的變化百分比來看，基板電阻的影響主要是反映在J-V圖的FF上。

An algorithm which extracts the substrate-resistance-free current-voltage (J-V) characteristics from large-area solar cells is proposed here. The effect of substrate resistance on device performance was also discussed.
We apply the algorithm to a set of real data measured from the devices with various device areas. The extracted results are matched with the real data. Besides, the extracted results of all devices are almost identical. Both observations cement the validity of the proposed algorithm.
The dependence of device performance and circuit-level parameters on the device length can be analyzed with this algorithm. Negative dependence of the power conversion efficiency (PCE), the short-circuit current (Jsc) and the fill factor (FF) of devices on the device length is observed while the open-circuit voltage (Voc) shows no dependence on the device length. This observed effect can be explained by the non-uniform potential distribution on the substrate.
Finally, we used the algorithm to quantify the effect of the substrate resistance and short-circuit current on device performance. We found that increases in percentage change of PCE, Jsc, FF, Rs and Rsh as sheet resistance of substrate or short-circuit current increase. The percentage change of FF is the maximum value, so we can conclude that substrate resistance affects FF most.

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