奈米實體層設計的良率及可繞度提昇｜國立清華大學博碩士論文庫

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研究生：	張豐願 Chang, Fong-Yuan
論文名稱：	奈米實體層設計的良率及可繞度提昇 Nanometer Physical Design for Yield and Routability Enhancement
指導教授：	蔡仁松 Tsay, Ren-Song
口試委員:	蔡仁松 Tsay, Ren-Song 麥偉基 Mak, Wai-Kei 王廷基 Wang, Ting-Chi 陳宏明 Chen, Hung-Ming 陳泰蓁 Chen, Tai-Chen 李毅郎 Li, Yih-Lang
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	79
中文關鍵詞：	實體層設計、繞線、製程規則
外文關鍵詞：	Maze, Redundant Wire, Cut-Demand, Nanometer Design Rule
相關次數：	點閱：3 下載：0
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現今的積體電路奈米製程, 遇到了很多的限制. 為了提升良率,在積體電路實體層設計時, 需要考量到製程上所遇到的限制. 這些限制增加了實體層設計的困難度, 本篇論文針對這些限制提出了解決方案,能夠提升實體層設計的可繞度及製程良率. 本論文主要提出了三個技術. 第一的技技術是利用插入額外繞線來增加良率. 第二個技術是針對扁平的設計區塊, 提出方法來提昇繞線資源的利用率. 第三個技術是一個繞線時就能同時考量製程規則的最短路徑繞線方法. 經由實驗結果驗證, 這些方法可以有效的提升實體層設計的可繞度及製程的良率.

In today’s nanometer IC (Integrated Circuit) processing, foundries are facing increasing challenges from process limitations that seriously impact the chip yield and reliability. To overcome these limits, numerous design rules are imposed by foundries to be followed in IC design, especially in physical design. Besides design rules, we need to handle some other manufacturing defects, such as wire opens and shorts, for higher chip yield rate. Thus, in this thesis we first introduce two techniques to deal with the process limitations. The first one focuses on handling design rules in maze routing. We propose a shortest path algorithm under nanometer design rules, called MANA. With the algorithm, most rule violations are prevented in maze routing instead of being resolved in post-processing. The second technique is to increase the chip yield by inserting redundant wires to tolerate wire opens. After completing the design routing, usually there are still remaining routing resources that can be used for redundant wire insertion. The proposed insertion algorithm can accurately consider the wire open and short simultaneously and guarantee yield increasing for each insertion. Besides the above two routing innovations, we also introduce a useful technique for routing resources allocation to improve routability. In current SoC (System on Chip), the aspect ratios of blocks in designs may vary much and the required resources in horizontal and vertical directions are different. Thus, we introduce an approach to allocate and consolidate routing resources considering directed routing resource demands, which can greatly increase routability especially for designs with thin areas. The goal for our proposed methods is to achieve high routability and chip yield for nanometer SoC designs.

Chapter 1.    Introduction    6
1.    Nanometer Wiring Rule Handling    6
2.    Yield Improvement by Redundant Wire Insertion    6
3.    Routability Enhancement by Resource Allocation    7
Chapter 2.    MANA: A Shortest Path MAze Algorithm under Separation and Minimum Length NAnometer Rules    7
1.    Introduction    8
2.    Wiring Rule Handling    10
2.1.    Nanometer Wiring Rule    10
2.2.    Traditional Rule Handling Methods    11
3.    A Shortest Path Algorithm under Separation and Minimum Length Nanometer Rules    13
3.1.    End-End Separation Rule Handling    13
3.2.    Path Length under Minimum Length Rule    15
3.3.    The MANA Algorithm    16
3.4.    Pruning Strategies and Time Complexity    19
3.5.    Proof of Shortest Path    22
3.6.    Discussion    23
4.    Enhanced MANA by Best Cost-First Expansion    24
4.1.    Motivation    24
4.2.    The Cost Function    25
4.3.    The Enhanced MANA Algorithm    26
4.4.    Discussion    28
5.    MANA on Gridless Routing    29
5.1.    Implicit Graph Routing    30
5.2.    Tile-Based Routing    31
6.    Experiments    32
6.1.    Integration    32
6.2.    Experiments    33
7.    Conclusion    37
Chapter 3.    Redundant Wire Insertion under Wire Open and Short    38
1.    Introduction    38
2.    Traditional Methods    40
3.    Yield Change    42
3.1.    Wire Short Analysis    42
3.2.    Yield Equation    43
4.    Problem Formulation    46
4.1.    The Redundant Wire Insertion Problem    46
4.2.    Redundant Wire Types    47
4.3.    Net Modeling    47
5.    The Redundant Wire Insertion Algorithm    48
5.1.    Problems    48
5.2.    The Algorithm    50
6.    Experimental Results    51
7.    Conclusion    55
Chapter 4.    Routing Resource Allocation and Consolidation    56
1.    Introduction    56
2.    Cut-Demand    59
2.1.    Aspect Ratio    59
2.2.    Traditional Resource Allocation    59
2.3.    H/V Cut-Demands    62
3.    Cut-Demand Prediction    62
4.    Routing Resource Allocation Methods    64
4.1.    Block Size Determination in Floorplanning    64
4.2.    Resource Consolidation in Placement    65
5.    Experimental Results    68
6.    Conclusion    72
Chapter 5.    Conclusion and Future Work    73
Chapter 6.    Reference    74


                                

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