在下一代無線通訊系統中，人們對於快速以及高品質資料傳輸的要求與日俱增，所以無線通訊應用需要更高速的通道編碼方式(Channel Coding Scheme)。而渦輪解碼器(Turbo code)為數位通訊系統裡最有名的通道編碼方式之一，其優點具有良好的錯誤更正能力(Outstanding Error Correct ability)，但是因為解碼時需要迭代次數(Iteration loop)，所以造成吞吐量(Throughput)下降。在本論文中，設計一個適用於前瞻性第三代合作夥伴計劃(3rd Generation Partnership Project, 3GPP-LTE-Advanced)規格可變動區塊大小的高速渦輪解碼器。首先，採用具有良好錯誤更正能力的最大事後機率演算法(Maximum A-Posteriori Algorithm, MAP)及採用平行區塊處理技術(Parallel Sub-block Processing)來提高平行度(High Parallelism)，以達到高吞吐量(High Throughput)的目的。此外設計出指令式交互連接器(Instruction-based Interconnection Circuit)及唯讀記憶體(Read Only Memory)來達到對於不同區塊大小的支援性。同時針對於高平行度所面臨到的記憶體衝突(Memory conflict)問題，提出無衝突導向的記憶體重置演算法(Contention-Free Oriented Memory Remapping Algorithm) 來產生適當的指令組合以搭配交互連結器的運作。透過此無衝突導向的記憶體重置演算法，所設計出來的渦輪解碼器將可在任何平行度的情況下運行，而達到減少最大事後機率處理器(MAP processor)的個數。最後，將所設計的渦輪解碼器利用UMC 90nm COMS製程、Faraday Cell Library與Faraday Memory Compiler方式實現，其合成(Synthesis)結果所設計的渦輪解碼器將在4次迭代的環境下最佳吞吐量可達到516Mb/s，其能量效能為0.2nJ/bit/iter。

The next complete evolution in wireless communications, the fourth-generation (4G), becomes more competitive and intensive. The services of wireless communication applications demand for high data rate and high quality. Therefore, the communication applications in the future may demand for a higher speed channel coding scheme. The Turbo code is one of the most popular channel coding schemes for digital communication systems.
This thesis proposes a high–throughput variable-block-size Turbo decoder for 3GPPLTE-
Advanced system. This work increases the parallelism degree by the parallel subblock processing to achieve the high–throughput requirement. In addition, the proposed Turbo decoder supports 188 different block sizes in the range 40∼6144 for 3GPP-LTEAdvanced specification. Besides, the contention-free oriented memory remapping algorithm provides contention-free technique with any parallelism degree. Meanwhile, the compatibility with variable block size is also accomplished by the instruction-based interconnection circuit and pre-processed instruction ROM. Finally, the proposed variableblock-size Turbo decoder was implemented and the proposed design was synthesized with the 90nm UMC CMOS technology. The Turbo decoder has the throughput of 516Mb/s with 4 iteration loops, and energy efficiency is 0.2 nJ/bit/iter.

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