隨著技術的進步，越來越的元件可以用單一晶片製作完成，但因為各元件的製程技術不同，使得要將所有元件以單一晶片完成變得困難且良率降低。因此系統模組封裝(SIP)技術便被提出使用，系統模組封裝使用不同製程製作元件，再將晶片排列堆疊，最後再以特殊接線方式連接不同晶片並封裝成單一晶片。
系統模組封裝使用特別的接線方式連接不同的晶片，不同晶片之間可以直接連接或透過導線架連接，接線的限制將受到晶片的旋轉位向及堆疊方式影響，當接線無法直接連接時便需要透過導線架來連接。本研究目的是要使得導線架所使用的繞線層數越少越好，本文先以徹底搜尋方式嘗試各種晶片堆疊及旋轉方式，加上不同接線方式組合以求得最少所需的繞線層數；另外提出了一個演算法以快速求得進似的最佳解。
第一種方式能求得導線架最少的繞線層數，第二種方式則快速求得近似解。根據實驗結果近似解的層數比最少的解最多只差一層，但可快速求得解節省許多時間及成本。

A special kind of wire connection is used for the System-in-Package (SIP). There is a close relation between the wire connection and leadframe. The locations of pads of nets are fixed, and the changes of the die rotation and layer location affect the connection of wires. Without connecting directly, leadframe is used to connect wires. We propose an algorithm to minimize the routing layers on leadframe. A fast heuristic algorithm was developed to find the approximate solution. Experimental results on a set of benchmark are reported to demonstrate the effectiveness of the proposed method. Also, we propose a heuristic method to shorten the computation time.

[1] Albert W. Lin, “Taiwan Foundry for System-In-Package (SIP),” Asia-South Pacific Design Automation Conference, 2000.
[2] Jani Miettinen, Matti Mantysalo, Kimmo Kaija, and Eero O. Ristolainen, “System Design Issues for 3D System-in-Package (SiP),” Electronic Components and Technology Conference, 2004.
[3] Jason Cong, Jie Wei, and Yan Zhang, “A Thermal-Driven Floorplanning Algorithm for 3D ICs,” International Conference on Computer Aided Design, 2003.
[4] Pun Hang Shiu, Ramprasad ravichandran, Siddharth Easwar, and Sung Kyu Lim, “Multi-layer Floorplanning for Reliable System-on-Package,” International Symposium on Circuits And Systems, 2004.