MDSC相量估計技術於電力系統保護數位電驛的比較分析

簡易檢索 / 詳目顯示

回結果列表

研究生：	莫翰拉傑 Mohanraj Bellie Subramani
論文名稱：	MDSC相量估計技術於電力系統保護數位電驛的比較分析 A Comparative Analysis of MDSC-Based Phasor Estimation Technique for Digital Relays in Power System Protection
指導教授：	朱家齊 CHU, CHIA-CHI
口試委員:	張淵智蘇昱丞吳有基連國龍黃維澤
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2025
畢業學年度：	113
語文別：	英文
論文頁數：	90
中文關鍵詞：	衰減直流分量、衰減直流分量、離散傅立葉變換、故障電流、諧波、相量估計
外文關鍵詞：	Decaying DC component, Decaying DC component, Discrete Fourier transform, Fault current, Harmonics, MDSC
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

衰減直流偏移(DDC) 對電力系統提出了重大挑戰，特別是在故障條件下，它會在故障電流波形中引入嚴重失真。這種失真使關鍵參數的可靠提取變得複雜，例如基頻分量的振幅和相位角，這對於保護繼電器的精確操作至關重要。DDC 的存在會延遲並降低相量估計的準確性，可能導致保護和控制機制發生故障或操作不當。保護繼電器在隔離故障部分和確保系統穩定性方面發揮著至關重要的作用，並依賴準確的訊號處理。DDC不僅影響波形，還會引入容易出錯的情況，可能導致誤跳脫或延遲故障清除，對系統的可靠性和安全性帶來嚴重風險。廣泛用於相量估計的基於傳統離散傅立葉變換(DFT) 的演算法特別容易受到故障電流中DDC 的影響。雖然DFT 在理想條件下有效，但當遇到衰減分量和諧波時，尤其是取樣率較低時，其效能會顯著惡化。低取樣率會加劇基於DFT 的估計值的不準確性，使其在瞬態快速變化和DDC 存在的情況下變得不可靠。這種限制直接影響了繼電器保護對故障快速、準確反應的能力，損害了故障分析的整體效果。因此，迫切需要能夠有效減輕DDC 影響並提高相量估計精度的先進技術，特別是在採樣率低和瞬態幹擾嚴重的環境中。
為了應對這些挑戰，所提出的多重延遲訊號消除（MDSC）濾波器已成為一種有前景的解決方案，為增強相量估計提供了創新方法。透過利用MDSC 濾波器，我們開發了三種先進方法來衰減DDC 分量，並能夠精確、快速地提取相量資訊。這些方法不僅提高了基頻相量估計的準確性，而且還證明了在受諧波、雜訊和非標稱頻率影響的條件下的穩健性。理論分析強調了這些基於MDSC 的方法的獨特優勢，包括它們以更高的取樣率有效執行的能力，從而克服了傳統DFT 方法面臨的限制。數值和模擬測試驗證了基於MDSC 的方法的優越性能，展示了它們在具有挑戰性的條件下準確估計相量的能力，為電力系統保護中更可靠、更高效的數位繼電器應用鋪平了道路。
這項關於衰減直流（DDC）估計的研究工作的成果如下：1）使用MDSC濾
波器的高頻調變技術：開發了一種先進的高頻調變技術，利用多重延遲訊號

消除（MDSC）濾波器進行精確估計衰減直流(DDC) 分量。2）利用MDSC濾波器進行下採樣高頻調變：提出了一種與高頻調變技術結合的下採樣方法，利用MDSC濾波器來提高計算效率，同時維持DDC估計的高精度。3）使用MDSC濾波器的基於四個半週期的演算法：設計了使用MDSC濾波器的基於四個半週期的演算法，能夠精確分割並改進對不同時間間隔內的DDC分量的分析。4) 採用MDSC 濾波器的新型下採樣DFT 方法：引入了一種使用源自MDSC濾波器的下採樣離散傅立葉變換(DFT) 方法進行DDC 估計的新方法，提高了計算衰減DC 分量的精度和魯棒性。這些貢獻共同提供了一個強大的框架，可以在各種實際應用中有效、準確地估計衰減直流分量。

Decaying DC offset (DDC) presents a significant challenge in power systems, particularly under fault conditions, where it introduces substantial distortion in the fault current waveform. This distortion complicates the reliable extraction of critical parameters, such as the magnitude and phase angle of the fundamental frequency component, which are essential for the precise operation of protective relays. The presence of DDC can delay and degrade the accuracy of phasor esti- mation, potentially leading to the malfunction or improper operation of protective and control mechanisms. Protective relays, which play a crucial role in isolating faulty sections and ensuring system stability, rely on accurate signal processing. DDC not only impacts the waveform but also introduces error-prone scenarios that may result in false trips or delayed fault clearance, posing serious risks to the system’s reliability and safety.
Traditional Discrete Fourier Transform (DFT)-based algorithms, widely used in phasor estimation, are particularly vulnerable to the effects of DDC in fault cur- rents. While DFT is effective under ideal conditions, its performance deteriorates significantly when confronted with decaying components and harmonics, especially when the sampling rate is low. Low sampling rates exacerbate the inaccuracies of DFT-based estimations, making them unreliable in scenarios with rapid tran- sient changes and DDC presence. This limitation directly impacts the ability of protective relays to respond promptly and accurately to faults, undermining the overall efficacy of fault analysis. Consequently, there is a critical need for advanced techniques that can effectively mitigate DDC effects and improve phasor estima- tion accuracy, particularly in environments with low sampling rates and significant transient disturbances.
To address these challenges, the proposed Multiple Delayed Signal Cancellation

(MDSC) filter has emerged as a promising solution, offering innovative methods for enhanced phasor estimation. By leveraging the MDSC filter, three advanced approaches have been developed to attenuate DDC components and enable pre- cise and rapid extraction of phasor information. These methods not only enhance the accuracy of fundamental frequency phasor estimation but also demonstrate robustness in conditions afflicted by harmonics, noise, and off-nominal frequen- cies. Theoretical analyses highlight the unique strengths of these MDSC-based methods, including their ability to perform effectively with higher sampling rates, thereby overcoming limitations faced by traditional DFT approaches. Numerical and simulation tests validate the superior performance of MDSC-based methods, showcasing their ability to accurately estimate phasors under challenging condi- tions, paving the way for more reliable and efficient digital relaying applications in power system protection.
The accomplishments of this research work on Decaying DC (DDC) estima- tion are as follows: 1) High-Frequency Modulation Technique using MDSC Filter: Developed an advanced high-frequency modulation technique that leverages the Multiple Delayed Signal Cancellation (MDSC) filter for accurate estimation of the Decaying DC (DDC) component. 2) Down-Sampling High-Frequency Modula- tion with MDSC Filter: Proposed a down-sampling methodology integrated with the high-frequency modulation technique, utilizing the MDSC filter to enhance computational efficiency while maintaining high accuracy in DDC estimation. 3) Four Half-Cycle-Based Algorithm using MDSC Filter: Designed a four-half-cycle- based algorithm employing the MDSC filter, enabling precise segmentation and improved analysis of the DDC component over distinct time intervals. 4) Novel Down-Sampling DFT Method with MDSC Filter: Introduced a new approach for DDC estimation using a Down-Sampling Discrete Fourier Transform (DFT) method derived from the MDSC filter, achieving enhanced precision and robust-

ness in calculating the Decaying DC component. These contributions collectively provide a robust framework for efficient and accurate estimation of the Decaying DC component in various practical applications.

Contents


Abstract (Chinese)    I

Abstract    III
Contents    VI
List of Figures    IX
List of Tables    XI
  Introduction    1
1    Background and Motivation    1
2    Phasor Estimation Techniques used in Digital Relays for Decaying
DC Removal    4
3    High-Frequency Modulation Technique using MDSC Filter    6
4    Down Sampling High-Frequency Modulation Technique using MDSC Filter    7
5    Four Half-Cycle Based Algorithm using MDSC Filter    8
  Phasor Estimation Techniques used in Digital Relays for Decaying DC Removal    10
1    Power System Protection    10
2    Digital and Numerical Relays    11
3    Phasor Estimation Methods    17
3.1    Introduction    17
3.2    Conventional DFT Method    20
3.3    Cosine Filter    22
3.4    Mimic Filter    23
3.5    Least-Square Methods    24
3.6    ANN    26
4    Multiple Delayed Signal Cancellation Method used for DDC Esti- mation    28
4.1    Single Phase MDSC Operator in Continuous-time    29
4.2    Single Phase MDSC Operator in Discrete-time    30
4.3    Recursive Realizations of MDSC Operators for Phasor Ex- tractions    32
5    Summary    38
  DDC Estimation Techniques using MDSC Filter    39
1    High-Frequency Modulation Technique using MDSC Filter (Pro- posed Method (a))    39
1.1    Introduction    39
1.2    DDC Estimation    40
1.3    Flowchart of the High-frequency Modulation Technique    44
2    Down-Sampling High-frequency modulation method using MDSC (Proposed Method (b))    45
2.1    Introduction    45
2.2    DDC Estimation    46
2.3    Flowchart of the High-frequency Modulation-based Down- Sampling Technique    49
3    Summary    50
  Four Half Cycle based Algorithm using MDSC Filter (Proposed Method (c)) :    51
1    Introduction    51
2    DDC Estimation    52
3    Flowchart of the Half Cycle based MDSC.    56
4    Performance Evaluation and Discussions    57
4.1    Computer Generated Signals    57
4.2    Basic Signal with Single DDC    58
4.3    Basic Signal with Two DDC    60
4.4    Basic Signal with Two DDCs and Harmonics    62
4.5    Basic Signal with Two DDCs and Harmonics and Noises    64
4.6    Basic Signal for Off-nominal Frequency    66
5    Real Transmission Line Simulation Studies    67
5.1    IEEE 9-Bus Power System    68
5.2    Test Case for Single Phase to Ground Fault    69
5.3    Test Case for Three Phase to Ground Fault    70
5.4    Summary    73
  Conclusion    76
Bibliography    80



List of Figures


1    Block diagram of basic numerical relays    13
2    Basic circuit for fault analysis    19
3    Fundamental component with DDC and harmonics    20
4    Magnitude of a fault current signal with/without DDC component.    22
5    Mimic circuit representation for eliminating DDC from the original
fault signal.    24
6    Block diagram basic ANN method.    27
7    Block diagram of MDSC: Direct form.    32
8    Block diagram of MDSC: Recursive form.    33
9    Bode plot for cMDSC when m=14    36
10    Bode plot for sMDSC when m=14.    36
11    Bode plot for cMDSC when m=16.    37
12    Bode plot for sMDSC when m=16.    37

1    Flowchart of the proposed method (a): High-frequency modulation.    45
2    Flowchart of the proposed method (b): High-frequency modulation based down-sampling.    50
1    Flowchart of the proposed method (c): Half cycle based MDSC.    56
2    Test case with 0.5 time constant: One DDC.    58
3    Test case with 5 time constant: One DDC.    59

4    Test case with 0.5 time constant: Two DDCs.    61
5    Test case with 5 time constant: Two DDCs.    62
6    Test case with 0.5 time constant: Two DDCs with harmonics.    63
7    Test cases with 5 time constant: Two DDCs with harmonics.    64
8    Test case with 0.5 time constant: Two DDCs with harmonics and
noise (40db).    65
9    Test case with 0.5 time constant: Two DDCs with harmonics and
noise (50db).    66
10    Test cases with 0.5 time constant: Off nominal frequency    67
11    IEEE 9 bus system.    68
12    Test case for IEEE 9-Bus System: LG fault with 0 (ohms).    69
13    Test case for IEEE 9-Bus System: LG fault with 5 (ohms).    70
14    Test case for IEEE 9-Bus System: LG fault with 5 (ohms) zoomed portion.    70
15    Test case for IEEE 9-Bus System: LLLG fault with 0 (ohms).    71
16    Test case for IEEE 9-Bus System: LLLG fault with 5 (ohms).    72
17    Test case for IEEE 9-Bus System: LLLG fault with 5 (ohms) zoomed portion.    72



List of Tables


1    Simulation Parameters.    28

1    Result comparison of 0.5 time constant- One DDC.    59
2    Result comparison of 5 time constant- One DDC.    59
3    Result comparison of 0.5 time constant- Two DDCs.    61
4    Result comparison of 5 time constant- Two DDCs    61
5    Result comparison of 0.5 time constant: Two DDC with harmonics    63
6    Result comparison of 5 time constant: Two DDC with harmonics.    63
7    Result comparison of 0.5 time constant: Two DDC with harmonics
and noise (40db).    65
8    Result comparison of 0.5 time constant: Two DDC with harmonics
and noise (50db).    65
9    Off nominal frequency condition.    67
10    Comparison result: LG fault with 0 (ohms).    69
11    Comparison result: LG fault with 5 (ohms).    71

                                

[1] A. T. Johns and S. K. Salman, Digital Protection for Power Systems, London, U.K:Inst. of Elect. Eng., 1995.
[2] A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Systems, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 1996.
[3] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, 3rd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2010.
[4] A. G. Phadke and J. S. Thorp, Computer Relaying for Power Systems. New York, NY. USA: Wiley, 1988.
[5] T. S.Sidhu, Xudong Zhang and V. Balamourougan, ”A new half- cycle phasor estimation algorithm,” IEEE Trans. on Power Del., vol. 20, no. 2, pp. 1299- 1305, April 2005.
[6] S. A. Gopalan, Y. Mishra, V. Sreeram, and H. H.-C. Iu, “An improved al- gorithm to remove dc offsets from fault current signals,” IEEE Trans. Power Del., vol. 32,no. 2, pp. 749–756, Apr. 2016.
[7] H. B. ElRefaie and A. I. Megahed, ”A novel technique to eliminate the effect of decaying DC component on DFT based phasor estimation,” IEEE PES General Meeting, Minneapolis, MN, USA, 2010, pp. 1-8.

[8] J.-C. Gu and S.-L. Yu, “Removal of dc offset in current and voltage signals using a novel Fourier filter algorithm,” IEEE Trans. Power Del., vol.15, no. 1, pp. 73–79, Jan. 2000.
[9] D. G. Hart, D. Novosel, and R. A. Smith, “Modified cosine filters,” U.S. and B. Kasztenny, “Adaptive measuring algorithm suppressing a decaying dc component for digital protective relays,” Elect.Power Syst. Res., vol. 60, pp. 99–105, Sep. 2001.
[10] B. Jafarpisheh, S. M. Madani, and S. M. Shahrtash, “A new DFT-based phasor estimation algorithm using high-frequency modulation,” IEEE Trans. Power Del., vol. 32, no. 6, pp. 2416–2423, Dec. 2017.
[11] B. Jafarpisheh, S. M. Madani, and S. Jafarpisheh, “Improved DFT-based phasor estimation algorithm using down-sampling,” IEEE Trans. Power Del., vol. 33, no. 6, pp. 3242–3245, Dec. 2018.
[12] S. Afrandideh, M. R. Arabhsahi, and S. M. Fazeli, “Two modified DFT-based algorithms for fundamental phasor estimation,” IET Gener., Transmiss. Dis- trib., vol. 16, pp. 3218–3229, 2022.
[13] Saeed Afrandideh, ”A Modified DFT-Based Phasor Estimation Algorithm Using an FIR Notch Filter,” IEEE Trans. Power Del., vol. 38, no. 2, April 2023.
[14] S.-H. Kang, D.-G. Lee, S.-R. Nam, P. A. Crossley, and Y.-C. Kang, “Fourier transform- based modified phasor estimation method immune to the effect of the dc offsets,” IEEE Trans. Power Del., vol. 24, no. 3, pp. 1104–1111, Jul. 2009.
[15] G. Benmouyal, “Removal of dc-offset in current waveforms using digital mimic filtering,” IEEE Trans. Power Del., vol. 10, no. 2, pp. 621–630, Apr. 1995.

[16] J. K. Hwang, C. K. Song and M. G. Jeong, ”DFT- Based Phasor Estimation for Removal of the Effect of Multiple DC.Components,” IEEE Trans. Power Del., vol.33, no. 6, pp. 2901-2909, Dec. 2018.
[17] M. Pazoki, ”A New DC-Offset Removal Method for Distance-Relaying Appli- cation Using Intrinsic Time-Scale Decomposition,” IEEE Trans. Power Del., vol. 33, no. 2, pp. 971-980, April 2018.
[18] Z. Jiang, S. Miao and P. Liu, ”A Modified Empirical Mode Decomposition Filtering- Based Adaptive Phasor Estimation Algorithm for Removal of Ex- ponentially Decaying DC Offset,” IEEE Trans. Power Del., vol. 29, no. 3, pp. 1326-1334, June 2014.
[19] M. R. Dadash Zadeh and Z. Zhang, ”A New DFT-Based Current Phasor Estimation for Numerical Protective Relaying,” IEEE Trans. on Power Del., vol. 28, no. 4, pp. 2172-2179, Oct. 2013.
[20] Y. Cho, C. Lee, G. Jang, and H. J. Lee, ”An Innovative Decaying DC Com- ponent Estimation Algorithm for Digital Relaying,” IEEE Trans. Power Del., vol. 24, no. 1, pp. 73-78, Jan. 2009.
[21] K. M.Silva and F. A. O. Nascimento, ”Modified DFT- Based Phasor Estima- tion Algorithms for Numerical Relaying Applications,” IEEE Trans. Power Del., vol. 33, no. 3, pp. 1165-1173, June 2018.
[22] J. L´azaro, J. Minambres, and M. Zorrozua, “Selective estimation of harmonic components in noisy electrical signals for protective relaying purposes,” Int.
J. Elect. Power Energy Syst., vol. 56, pp. 140–146, 2014.

[23] A. Ashrafian, M. Mirsalim, and M. A. Masoum, “An adaptive recursive wavelet-based algorithm for real-time measurement of power system variables

during off-nominal frequency conditions,” IEEE Trans. Ind. Inform., vol. 14, no. 3, pp. 818–828, Mar. 2018.
[24] P. D. Achlerkar and B. K. Panigrahi, “Assessment of DC offset in fault cur- rent signal for accurate phasor estimation considering current transformer response,” IET Sci., Meas. Technol., vol. 13, pp. 403–408, 2018.
[25] Y. Guo, M. Kezunovic, and D. Chen, “Simplified algorithms for removal of the effect of exponentially decaying dc offset on the Fourier algorithm,” IEEE Trans. Power Del., vol. 18, no. 3, pp. 711–717, Jul. 2003.
[26] T. P. S. Bains and M. R. Dadash Zadeh, “Enhanced phasor estimation tech- nique for fault location in series compensated lines,” IEEE Trans. Power Del., vol. 30, no. 4, pp. 2058–2060, Dec. 2015.
[27] K. W. Min and S. Santoso, “DC offset removal algorithm for improving loca- tion estimates of momentary faults,” IEEE Trans. Smart Grid, vol. 9, no. 6,
pp. 5503–5511, Nov. 2018.

[28] L. Fan, “Least squares estimation and Kalman filter based dynamic state and parameter estimation,” Proc. IEEE Power Energy Soc. Gen. Meeting, 2015,
pp. 1–5.

[29] L. Xiong, X. Liu, C. Zhao, and F. Zhuo, “A fast and robust real-time detection algorithm of decaying DC transient and harmonic components in three-phase systems,” IEEE Trans. Power Electron., vol. 35, no. 4, pp. 3332–3336, Apr. 2020.
[30] B. R. Kumar and A. Kumar, “Mitigation of the DC offset by a sub-cycle sample method M-Class PMUs,” IEEE Trans. Power Del., vol. 34, no. 2, pp. 780–783, Apr. 2019.

[31] H. Hajizadeh, S.-A. Ahmadi, and M. Sanaye-Pasand, “An analytical fast de- caying DC mitigation method for digital relaying applications,” IEEE Trans. Power Del., vol. 36, no. 6, pp. 3529–3537, Dec. 2021.
[32] B. R. Kumar, A. Mohapatra, and S. Chakrabarti, “A novel sub-cycle based method for estimation of decaying DC component and fundamental phasor,” IEEE Trans. Instrum. Meas., vol. 70, pp. 1-10, 2021.
[33] H. Yu, Z. Jin, H. Zhang, and V. Terzija, “A phasor estimation algorithm robust to decaying DC component,” IEEE Trans. Power Del., vol. 37, no. 2,
pp. 860–870, Apr. 2022.

[34] S. A. Saleh, E. Ozkop, A. Al-Durra, T. Hill, J. Meng, and M. E. Valdes, “On the assessment of sampling rate impacts on responses of digital protective relays,” IEEE Trans. Ind. Appl., pp. 1–11, 2023.
[35] S. Gude and C.-C. Chu, ”Three-phase PLLs by using frequency adaptive multiple delayed signal cancellation prefilters under adverse grid conditions,” IEEE Trans. Ind. Appl., vol. 54, no. 4, pp. 3832-3844, July-August 2018.
[36] S. Gude and C.-C. Chu, ”Dynamic performance improvement of multiple delayed signal cancellation filters based three-phase enhanced-PLL,” IEEE Trans. Ind. Appl., vol. 54, no. 5, pp. 5293-5305, Sept.-Oct. 2018.
[37] S. C. Gulipalli, S. Gude, S.-C. Peng and C.-C. Chu, “Multiple Delayed Signal Cancellation Filter-Based Enhanced Frequency-Locked Loop Under Adverse Grid Conditions,” IEEE Trans. on Ind. Appl., vol. 58, no. 5, pp. 6612-6628, Sept.-Oct. 2022.
[38] Y. F. Wang and Y. W. Li, “Analysis and digital implementation of cascaded delayed signal cancellation,” IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1067–1080, Apr. 2011.

[39] Nguyen HT, El Moursi MS, Al Hosani K, Al-Sumaiti AS and Al Durra A. ”Independent Time-Delay Signal Cancellation for Fast Harmonic-Sequence Filters Targeting Arbitrary Sequences and Frequencies,” IEEE Trans. Ind. Informatics., vol. 20, no. 7, pp. 9330-9342, July 2024.
[40] X. Cheng, W. J. Lee, and X. Pan, “Modernizing substation automation sys- tems: Adopting IEC standard61850 for modeling and communication,” IEEE Ind. Appl. Mag., vol. 23, no 1, pp. 42–49, Jan./Feb. 2017.
[41] M. Sharma, L. Nguyen, S. Kuber, and D. Baradi, “Testing IEC-61850 sampled values-based transformer differential protection scheme,” Proc. 74th IEEE Conf. Protective Relay Engineers, College Station, TX, USA, 2021, pp. 1–8.
[42] S. Gude and C. -C. Chu, ”Single-Phase Enhanced Phase-Locked Loops Based on Multiple Delayed Signal Cancellation Filters for Micro-Grid Applications,” IEEE Trans. Ind. Appl., vol. 55, no. 6, pp. 7122-7133, Nov.-Dec. 2019.
[43] M. Bellie Subramani, S. Gude, C. -C. Chu and J. M. Guerrero, ”A Compara- tive Analysis of MDSC-Based Phasor Estimation Technique for Digital Relays in Power System Protection,” IEEE Access, vol. 12, pp. 162327-162346, 2024.
[44] A. Yazdani and R. Iravani, Voltage-Sourced Converters in Power Systems: Modeling, Control, and Applications, Hoboken, NJ, USA: Wiley, 2010.
[45] S. Golestan, J. M. Guerrero, and J. C. Vasquez, “A nonadaptive window- based PLL for single-phase applications,” IEEE Trans. Power Electron., vol. 33, no. 1, pp. 24–31, Jan. 2018.
[46] P. Sumathi and P. A. Janakiraman, “Integrated phase-locking scheme for SDFT-based harmonic analysis of periodic signals,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 1, pp. 51–55, Jan. 2008.

[47] M. Parker, Digital Signal Processing 101: Everything You Need to Know to Get Started, 2nd Ed., Newnes, Oxford, UK, 2017.
[48] M. B. Subramani, S. Gude and C. C. Chu, “A New Modified MDSC based Phasor Estimation Technique for Decaying DC offset Removal,” IEEE 3rd Int. Conf. on Smart Technologies for Power, Energy and Control (STPEC) Bhubaneswar, India Dec 2023, pp. 1–6.
[49] M. B. Subramani, S. Gude and C. C. Chu, “A Modified MDSC based Phasor Estimation Technique for Power System Protection,” IEEE 3rd Int. Conf. on Smart Technologies for Power, Energy and Control (STPEC) Bhubaneswar, India Dec 2023, pp. 1–6.
[50] P. M. Anderson and A. A. Fouad, Power System Control and Stability. Pis- cataway, NJ: IEEE Press/Wiley, 2003.
[51] M. B. Subramani, S. Gude and C. C. Chu, ”A New Modified Down-sampling DFT based Phasor Estimation Technique for Power System Protective Re- lays,” IEEE/IAS 60th Industrial and Commercial Power Systems Technical Conference (I&CPS), Las Vegas, NV, USA, 2024, pp. 1-8.
[52] The Institution of Electrical Engineers, Power System Protection, vol. 1,2,3 and 4, Short Run Press Ltd, 1995.
[53] Elmore, W.A., Protective Relaying Theory and Applications, Marcel Dekker Inc., 2004.
[54] IEEE Tutorial Course, Microprocessor Relays and Protection Systems, The Institute of Electrical and Electronic Engineers, 1988.
[55] Ziegler, G., Numerical Distance Protection Principles and Applications, Siemens AG, 1999.

[56] Kirpane, R.; Bedekar, P.P. ”Removal of DC offset using digital mimic filter- ing technique”. Proceedings of the 2016 International Conference on Global Trends in Signal Processing, Information Computing and Communication (ICGTSPICC), Jalgaon, India, 22–24 December 2016; pp. 470–475.
[57] Mohammadi, S.; Mahmoudi, A.; Kahourzade, S.; Yazdani, A.; Shafiullah, G. Decaying DC Offset Current Mitigation in Phasor Estimation Applications: A Review. Energies 2022, 15, 5260.
[58] Sachdev, M.S.; Baribeau, M.A. ”A new algorithm for digital impedance re- lays”. IEEE Trans. Power Appar. Syst. 1979, PAS-98, 2232–2240.
[59] Jafarian, P.; Sanaye-Pasand, M. ”An adaptive phasor estimation technique based on LES method using forgetting factor”.Proceedings of the 2009 IEEE Power and Energy Society General Meeting (PES ’09), Calgary, AB, Canada, 26–30 July 2009; pp. 1–8.
[60] Jafarian, P.; Sanaye-Pasand, M. Weighted least error squares based vari- able window phasor estimator for distance relaying application. IET Gener. Transm. Distrib. 2011, 5, 298–306.
[61] Da Silva, C.D.; Junior, G.C.; Mariotto, L.; Marchesan, G. Phasor estimation in power systems using a neural network with online training for numerical relays purposes. IET Sci. Meas. Technol. 2015, 9, 836–841.
[62] Imran, M.; Alsuhaibani, S.A. A Neuro-Fuzzy Inference Model for Diabetic Retinopathy Classification. In Intelligent Data Analysis for Biomedical Ap- plications; Elsevier: Amsterdam, The Netherlands, 2019; pp. 147–172.
[63] Lana da Silva, C.D.; Cardoso, G.; de Morais, A.P.; Marchesan, G.; Kaehler Guarda, F.G. A continually online trained impedance estimation algorithm for

transmission line distance protection tolerant to system frequency deviation.
Electr. Power Syst. Res. 2017, 147, 73–80.

[64] Kim, S.B.; Sok, V.; Kang, S.H.; Lee, N.H.; Nam, S.R. A study on deep neu- ral network-based DC Offset removal for phase estimation in power systems. Energies 2019, 12, 1619.
[65] K. Hasan, S. T. Meraj, M. M. Othman, M. S. H. Lipu, M. A. Hannan and K.
M. Muttaqi, ”Savitzky–Golay Filter-Based PLL: Modeling and Performance Validation,” IEEE Trans. on Instrum. Meas., vol. 71, pp. 1-6, 2022.
[66] Y. Xia, Y. He, K. Wang, W. Pei, Z. Blazic and D. P. Mandic, ”A Complex Least Squares Enhanced Smart DFT Technique for Power System Frequency Estimation,” in IEEE Trans. on Power Del., vol. 32, no. 3, pp. 1270-1278, June 2017.

簡易檢索 / 詳目顯示

相關論文