近年來，由於黃光微影製程遭受到物理限制，使得元件的最小線寬無法無止境的縮小，微電子工業已面臨到難以追隨摩爾定律(Moore’s law)的瓶頸。然而，為了使電子產品能夠滿足輕、薄、短、小的需求，研究方向已逐漸轉往新摩爾定律(more than Moore’s law)的系統級封裝(system-in-package, SiP)發展。系統級封裝結構主要是藉由直通矽晶穿孔(through silicon via, TSV)或覆晶(flip-chip)等方式，透過晶片堆疊或並排達到整合的目的，此舉可避免元件線寬阻擋電子元件之發展。在本研究中，將提出一使用內埋式晶圓級封裝且具雙面電訊接點與堆疊晶片之結構。此結構之扇出(fan-out)的特性可解決晶片與印刷電路板墊片間距不一致的連接問題。
首先，以有限單元法探討此結構之散熱特性，同時也與傳統晶圓級封裝結構之散熱行為進行比較。由於本研究所提出之結構其面積較大且具有熱傳特性佳之矽載板，可提供另一散熱途徑進行散熱，有效降低封裝結構之接面熱阻至39 °C/W，而傳統晶圓級封裝結構之熱阻為49 °C/W，此結構可大大提升電子封裝的散熱能力。根據雙面電訊接點且雙晶片堆疊結構在熱循環負載中之熱機械行為，對於錫球、重新佈線層之整體可靠度評估可藉由有限單元法進行研究。使用較軟的應力緩衝材料並搭配熱膨脹係數與印刷電路板接近的載板，可使錫球的壽命高於1,000循環。而基於本研究提出的設計準則，本研究提出之封裝結構可成功應用在大尺寸晶片之封裝上，並得到封裝產業能接受的可靠度壽命。此外，在重新佈線層之設計方面，導線與墊片之連接角度，建議與主要熱膨脹係數不匹配方向平行，且此角度對應力的影響極為敏感；而U型彎曲結構可吸收導線和填充材料的膨脹，以減緩晶片墊片上的應力集中情形。此外，第一重新佈線層上的熱機械行為並不隨導線與墊片之連接角度和U型彎曲結構而有所改變，但使用較硬的導線保護層材料可減少第一重新佈線層的變形，進而減緩晶片墊片的應力集中現象。
模擬設計法(design-on-simulation)對於電子封裝產業發展新型封裝結構有其必要性。未來微電子封裝之整體設計、熱分析和結構可靠度評估可藉由此數值方法搭配適當的實驗驗證，來進行研發與設計。此分析流程可有效的減少新興電子產品的上市時程與製造成本。

Recently, physical limitations restrict the development of microelectronic industry following Moore’s law. To achieve high performance, small form factor and lightweight application, the electronic packaging has developed following more than Moore’s law which is fulfilled by system-in-package (SiP) or 3D packaging approaches. This research proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. It can resolve the problem of assembling fine-pitched chip to coarse-pitched PCB through redistribution layer (RDL).
The thermal performance of the proposed packaging structure is examined and discussed by using finite element (FE) analysis. The thermal performance of the WLCSP is compared with the proposed structure. It indicates that the thermal resistance is reduced from 49 °C/W to 39 °C/W, because the proposed packaging structure has a larger size silicon carrier to improve the capability of heat dissipation. According to the thermo-mechanical behavior of the double-sided with double-chip stacking structure during thermal cycling loading, the overall reliability assessment for solder joints and RDLs through FE analysis are studied. The application of soft lamination material and the selection of carrier material whose CTE is close to that of PCB can effectively enhance the reliability of solder joints more than 1,000 cycles. Base on the proposed design guideline, the large dies and NAND stacked flash dies are successfully applied on the proposed structure, and the life time predicted in this research is accepted by most electronic packaging industries. Besides, the double-side capability is applied on the proposed structure; the first and second RDLs are established in FE model. The strain values of the first RDL are not varied along with changing of trace layout. Stiff passivation material can prevent the deformation of the first RDL caused by out-of-plane movement to diminish the equivalent plastic strain at copper via. For the second RDL, the direction of the trace/pad junction which is parallel to the major direction of the CTE mismatch is recommended. The curved portion can absorb the expansion of metal line and filler material, and the stress concentration happens at via is reduced.
The design-on-simulation (DOS) methodology is necessary in developing novel packaging structure in the electronic packaging industry. The overall design, thermal analysis, and structural reliability assessment for future microelectronic packaging can be analyzed through numerical method with suitable validation. The analytic procedure can effectively reduce time-to-market and fabrication cost of new electronic devices.

[1] R. R. Tummala, "SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade," IEEE Transactions on Advanced Packaging, vol. 27, pp. 241-249, 2004.
[2] C. S. Tan, E. J. Gutmann, and L. R. Reif, Wafer Level 3-D ICs Process Technology, 1st ed., New York, Springer, 2008.
[3] G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, pp. 114-117, 1965.
[4] G. Q. Zhang, M. Graef, and F. van Roosmalen, "The rationale and paradigm of "more than Moore"," 56th Electronic Components and Technology Conference, San Diago, CA, USA, May 30-Jun. 2, 2006
[5] J. H. Lau, "Evolution and outlook of TSV and 3D IC/Si integration," 12th Electronics Packaging Technology Conference, Singapore, Dec. 8-10, 2010
[6] F. Carson, H. T. Lee, J. H. Yee, L. Punzalan, and E. Fontanilla, "Die to die copper wire bonding enabling low cost 3D packaging," 61st Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, May 31-June 3, 2011
[7] C. S. Selvanayagam, John H. Lau, Z. X, S. K. W. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps," 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, May 27-30, 2008
[8] K. Tanida, M. Umemoto, T. Morifuji, R. Kajiwara, T. Ando, Y. Tomita, N. Tanaka, and K. Takahashi, "Au bump interconnection in 20 µm pitch on 3D chip stacking technology," Japanese Journal of Applied Physics, vol. 42, pp. 6390-6395, 2003.
[9] K. Takahashi, M. Umemoto, N. Tanaka, K. Tanida, Y. Nemoto, Y. Tomita, M. Tago, and M. Bonkohara, "Ultra-high-density interconnection technology of three-dimensional packaging," Microelectronics Reliability, vol. 43, pp. 1267-1279, 2003.
[10] J. U. Meyer, T. Stieglitz, O. Scholz, W. Haberer, and H. Beutel, "High density interconnects and flexible hybrid assemblies for active biomedical implants," IEEE Transactions on Advanced Packaging, vol. 24, pp. 366-374, 2001.
[11] W. C. Lo, Y. H. Chen, J. D. Ko, T. Y. Kuo, Y. C. Shih, and S. T. Lu, "An innovative chip-to-wafer and wafer-to-wafer stacking," 56th Electronic Components and Technology Conference, San Diego, CA, USA, May 30-Jun. 2, 2006
[12] T. Y. Kuo, S. M. Chang, Y. C. Shih, C. W. Chiang, C. K. Hsu, C. K. Lee, C. T. Lin, Y. H. Chen, and W. C. Lo, "Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost," 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, May 27-30, 2008
[13] J. H. Lau, "TSV manufacturing yield and hidden costs for 3D IC integration," 60th Electronic Components and Technology Conference, Las Vegas, NV, USA, Jun. 1-4, 2010
[14] T. H. Kuo, Y. F. Su, C. J. Wu, and K. N. Chiang, "Stress/stain assessment and reliability prediction of through silicon via and trace line structures of 3D packaging," 12th Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), Linz, Austria, Apr. 18-20, 2011
[15] M. C. Hsieh and C. K. Yu, "Thermo-mechanical simulations for 4-layer stacked IC packages," 9th Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems (EuroSimE), Freiburg, Germany, Apr. 20-23, 2008
[16] M. C. Hsieh, C. K. Yu, and W. Lee, "Effects of geometry and material properties for stacked IC package with spacer structure," 10th Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystem (EuroSimE), Delft, Nederland, Apr. 26-29, 2009
[17] C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang, "Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique," Microelectronic Engineering, vol. 88, pp. 739-744, 2011.
[18] P. C. Chen, Y. F. Su, S. Y. Yang, S. Y. Liang, and K. N. Chiang, "Determination of initial crack strength of silicon die using acoustic emission technique," Journal of Electronic Materials, pp. 1-10, 2015/05/12 2015.
[19] K. X. Hu, C. P. Yeh, B. Doot, A. F. Skipor, and K. W. Wyatt, "Die cracking in flip-chip-on-board assembly," 45th Electronic Components and Technology Conference, Las Vegas, NV, USA, May 21-24, 1995
[20] S. F. Popelar, "An investigation into the fracture of silicon die used in flip chip applications," 4th International Symposium on Advanced Packaging Materials, Braselton, GA, USA, Mar. 15-18, 1998
[21] K. Sakuma, K. Sueoka, S. Kohara, K. Matsumoto, H. Noma, T. Aoki, Y. Oyama, H. Nishiwaki, P. S. Andry, C. K. Tsang, J. U. Knickerbocker, and Y. Orii, "IMC bonding for 3D interconnection," 60th Electronic Components and Technology Conference, Las Vegas, NV, USA, Jun. 1-4, 2010
[22] M. Y. Tsai, C. H. Chen, and C. S. Lin, "Test methods for silicon die strength," Journal of Electronic Packaging, vol. 128, pp. 419-426, 2006.
[23] M. Y. Tsai and C. H. Chen, "Evaluation of test methods for silicon die strength," Microelectronics Reliability, vol. 48, pp. 933-941, 2008.
[24] C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via," Microelectronic Engineering, vol. 87, pp. 505-509, 2010.
[25] P. C. Chen, Y. F. Su, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Evaluation of die strength by using finite element method with experiment validation," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, pp. 1152-1158, 2014.
[26] M. Brunnbauer, E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi, "An embedded device technology based on a molded reconfigured wafer," 56th Electronic Components and Technology Conference, San Diego, CA, USA, May 30-Jun. 2, 2006
[27] T. Meyer, G. Ofner, S. Bradl, M. Brunnbauer, and R. Hagen, "Embedded Wafer Level Ball Grid Array (eWLB)," 10th Electronics Packaging Technology Conference, Singapore, Dec. 9-12, 2008
[28] N. Motohashi, T. Kimura, K. Mineo, Y. Yamada, T. Nishiyama, K. Shibuya, H. Kobayashi, Y. Kurita, and M. Kawano, "System in wafer-level package technology with RDL-first process," 61th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, May 31-Jun. 3, 2011
[29] M. C. Yew, C. A. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and K. N. Chiang, "Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging," IEEE Transactions on Advanced Packaging, vol. 32, pp. 390-398, 2009.
[30] J. Zheng, Z. Zhang, Y. Chen, and J. Shi, "3D stacked package technology and its application prospects," International Conference on New Trends in Information and Service Science, Beijing, China, Jun. 30-Jul. 2, 2009
[31] J. Kim, K. Lee, D. Park, T. Hwang, K. Kim, D. Kang, J. Kim, C. Lee, C. Scanlan, C. J. Berry, C. Zwenger, L. Smith, M. Dreiza, and R. Darveaux, "Application of through mold via (TMV) as PoP base package," 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, May 27-30, 2008
[32] A. Yoshida, S. Wen, W. Lin, J. Kim, and K. Ishibashi, "A study on an ultra thin PoP using through mold via technology," 61th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, May 31-Jun. 3, 2011
[33] Y. Jin, X. Baraton, S. W. Yoon, Y. Lin, P. C. Marimuthu, V. P. Ganesh, T. Meyer, and A. Bahr, "Next generation eWLB (embedded wafer level BGA) packaging," 12th Electronics Packaging Technology Conference, Singapore, Dec. 8-10, 2010
[34] S. W. Yoon, A. Bahr, X. Baraton, P. C. Marimuthu, and F. Carson, "3D eWLB (embedded wafer level BGA) technology for 3D-packaging/3D-SiP (Systems-in-Package) applications," 11th Electronics Packaging Technology Conference, Singapore, Dec. 9-11, 2009
[35] D. Manessis, L. Boettcher, A. Ostmann, R. Aschenbrenner, and H. Reichl, "Innovative approaches for realisation of embedded chip packages - Technological challenges and achievements," 59th Electronic Components and Technology Conference, San Diego, CA, USA, May 26-29, 2009
[36] K. F. Becker, T. Braun, A. Neumann, A. Ostmann, E. Coko, M. Koch, V. Bader, R. Aschenbrenner, and H. Reichl, "A New Wafer Level Packaging Approach Encapsulation, Metallization and Laser Structuring for Advanced System in Package Manufacturing," Journal of Electronic Packaging, vol. 127, pp. 1-6, 2005.
[37] T. Braun, K. Becker, S. Voges, T. Thomas, R. Kahle, V. Bader, J. Bauer, K. Piefke, R. Kruger, R. Aschenbrenner, and K. Lang, "Through mold vias for stacking of mold embedded packages," 61th Electronic Components and Technology Conference, Lake Buena Vista, FL, USA, May 31-June 3, 2011
[38] S. W. Ho, F. M. Daniel, L. Y. Siow, W. H. SeeToh, W. S. Lee, S. C. Chong, and V. S. Rao, "Double side redistribution layer process on embedded wafer level package for package on package (PoP) applications," 12th Electronics Packaging Technology Conference, Singapore, Dec. 8-10, 2010
[39] V. Kripesh, V. S. Rao, A. Kumar, G. Sharma, C. H. Khoong, X. Zhang, Y. M. Khoo, N. Khan, and J. H. Lau, "Design and development of a multi-die embedded micro wafer level package," 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, May 27-30, 2008
[40] F. Zudock, T. Meyer, M. Brunnbauer, and A. Wolter, "Semiconductor device," Infineon, US 8093711, 2012.
[41] R. A. Pagaila, Y. Lin, and S. U. Yoon, "Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier " STATS CHIPPAC, LTD, US 8822281, 2014.
[42] M. C. Yew, C. A. Yuan, C. Y. Chou, and K. N. Chiang, "3D electronic packaging structure having a conductive support substrate," Advanced Chip Engineering Technologies Inc, US 7884464, 2011.
[43] M. C. Yew, C. C. Chiu, K. N. Chiang, and W. K. Yang, "3D electronic packaging structure with enhanced grounding performance and embedded antenna," Advanced Chip Engineering Technologies Inc., US 20080142941, 2008.
[44] C. Y. Chou, M. C. Yew, and K. N. Chiang, "Thin stack package using embedded-type chip carrier," National Tsing Hua University, I395318 (中華民國發明專利), 2013.
[45] J. H. Lau, Ball grid array technology, New York, McGraw-Hill, 1995.
[46] J. H. Lau, Flip chip technologies, Boston, McGraw-Hill, 1996.
[47] J. H. Lau, Electronic packaging: design, materials, process, and reliability New York, McGraw-Hill, 1998.
[48] J. H. Lau and Y. H. Pao, Solder joint reliability of BGA, CSP, Flip chip, and fine pitch SMT assemblies, New York, McGraw-Hill, 1997.
[49] L. F. Coffin, "A study of the effects of cycle thermal stress on a ductile metal " Transactions of ASME, vol. 76, pp. 931-950, 1954.
[50] S. S. Manson, "Behavior of materials under conditions of thermal stress," National Advisory Committee for Aeronautics-Technical Note 2933, pp. 317-350, 1953.
[51] S. S. Manson, Thermal stress and low-cycle fatigue, New York, McGraw-Hill, 1966.
[52] H. D. Solomon, "Fatigue of 60/40 Solder," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 9, pp. 423-432, 1986.
[53] X. Q. Shi, H. L. J. Pang, W. Zhou, and Z. P. Wang, "Low cycle fatigue analysis of temperature and frequency effects in eutectic solder alloy," International Journal of Fatigue, vol. 22, pp. 217-228, 2000.
[54] S. F. Popelar, "A parametric study of flip chip reliability based on solder fatigue modelling," 21st International Electronics Manufacturing Technology Symposium, Austin, TX, USA, Oct. 13-15, 1997
[55] J. P. Clech, "BGA, flip-chip and csp solder joint reliability: of the importance of model validation," ASME InterPACK, Hawaii, USA, Jun. 13-19, 1999
[56] J. H. Lau, S. Golwalkar, S. Erasmus, R. Surratt, and P. Boysan, "Experimental and analytical studies of 28-pin thin small outline package (TSOP) solder-Joint reliability," Journal of Electronic Packaging, vol. 114, pp. 169-176, 1992.
[57] C. T. Peng, C. M. Liu, J. C. Lin, H. C. Cheng, and K. N. Chiang, "Reliability analysis and design for the fine-pitch flip chip BGA packaging," IEEE Transactions on Components and Packaging Technology, vol. 27, pp. 684-693, 2004.
[58] C. M. Liu, C. C. Lee, and K. N. Chiang, "Enhancing the reliability of wafer level packaging by using solder joints layout design," IEEE Transactions on Components and Packaging Technologies, vol. 29, pp. 877-885.
[59] M. Gonzalez, B. Vandevelde, M. V. Bulcke, C. Winters, E. Beyne, Y. I. Lee, L. Larson, B. R. Harkness, M. Mohamed, H. Meynen, and E. Vanlathem, "An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration," 53rd Electronic Components and Technology Conference, New Orleans, LA, USA, May 27-30, 2003
[60] F. X. Che, T. H. Low, H. L. Pang, W. C. Lin, C. L. Chiang, and T. K. Yang, "Modeling thermo-mechanical reliability of bumpless flip chip package," 54th Electronic Components and Technology Conference, Las Vegas, NV, USA, Jun. 1-4, 2004
[61] W. Engelmaier, "A new ductility and flexural fatigue test method for copper foil and flexible printed wiring," IPC-TP-204, Institute for Interconnecting and Packaging Electronic Circuits, Evanston, IL, USA, 1978.
[62] W. Engelmaier, "A Method for the Determination of Ductility for Thin Metallic Material," in Formability of Metallic Material — 2000 A.D., ASME STP 753, J. R. N. a. B. A. Niemeier, Ed., ed Philadelphia: American Society for Testing and Materials, 1982, , pp. 279-295.
[63] W. Engelmaier, "Results of the IPC Copper Foil Ductility Round-Robin Study," in Testing of Metallic and Inorganic Coating, ASTM STP 947, W. B. H. a. G. A. D. Bari, Ed., ed Philadelphia: American Society for Testing and Materials, 1982.
[64] W. Engelmaier, "Flexural Fatigue and Ductility, Foil," IPC-TM-650, The Institute for Interconnecting and Packaging Electronic Circuits, Evanston, IL, USA, 1980.
[65] M. C. Yew, M. Tsai, D. C. Hu, W. K. Yang, and K. N. Chiang, "Reliability analysis of a novel fan-out type WLP," Soldering & Surface Mount Technology, vol. 21, pp. 30-38, 2009.
[66] R. Iannuzzelli, "Predicting plated-through-hole reliability in high temperature manufacturing processes," 41st Electronic Components and Technology Conference, Atlanta, GA, USA, May 11-16, 1991
[67] R. V. Pucha, G. Ramakrishna, S. Mahalingam, and S. K. Sitaraman, "Modeling spatial strain gradient effects in thermo-mechanical fatigue of copper microstructures," International Journal of Fatigue, vol. 26, pp. 947-957, 2004.
[68] K. M. Chen, K. H. Houng, and K. N. Chiang, "Thermal resistance analysis and validation of flip chip PBGA packages," Microelectronics Reliability, vol. 46, pp. 440-448, 2006.
[69] C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," ASME InterPACK, Vancouver, British Columbia, Canada, Jul. 8-12, 2007
[70] "Integrated circuits thermal measurement method-electrical test method (single semiconductor device)," JEDEC JESD51-1, EIA & JEDEC Solid State Technology Association, 1995.
[71] Y. Xi and E. F. Schubert, "Junction-temperature measurement in GaN ultraviolet light-emitting diodes using diode forward voltage method," Applied Physics Letters, vol. 85, pp. 2163-2165, 2004.
[72] W. H. Chi, T. L. Chou, C. N. Han, and K. N. Chiang, "Analysis of thermal performance of high power light emitting diodes package," 10th Electronics Packaging Technology Conference, Singapore, Dec. 9-12, 2008
[73] W. H. Chi, T. L. Chou, S. Y. Yang, C. N. Han, and K. N. Chiang, "Analysis of thermal performance for high power light emitting diodes lighting module," 10th International Conference on Electronics Packaging Technology, Kyoto, Japan, April 14-16, 2009
[74] S. L. Kuo, C. K. Liu, M. J. Dai, C. K. Yu, H. C. Chien, and C. Y. Hsu, "Characteristics of Thermal Resistance for High Power LEDs," 10 th Electronics Packaging Technology Conference, Singapore, Dec. 9-12, 2008
[75] Y. F. Su, S. Y. Yang, T. Y. Hung, C. C. Lee, and K. N. Chiang, "Light degradation test and design of thermal performance for high-power light-emitting diodes," Microelectronics Reliability, vol. 52, pp. 794-803, 2012.
[76] K. N. Chiang and C. A. Yuan, "An overview of solder bump shape prediction algorithms with validations," IEEE Transactions on Advanced Packaging, vol. 24, pp. 158-162, 2001.
[77] F. P. Incropera and D. P. DeWitt, Fundamentals of heat and mass transfer, 5th ed., New York, Wiley 2002.
[78] G. N. Ellison, Thermal computations for electronic equipment, R. E. Krieger Publishing Company, Malabar, FL, 1989.
[79] W. H. Chen, H. C. Cheng, and H. A. Shen, "An effective methodology for thermal characterization of electronic packaging," IEEE Transactions on Components and Packaging Technologies, vol. 26, pp. 222-232, 2003.
[80] J. A. Collins, Failure of materials in mechanical design: analysis, prediction, prevention, 2nd ed., New York, John Wiley & Sons, 1993.
[81] W. H. McAdams, Heat transmission, New York, McGraw-Hill, 1954.
[82] "Test boards for area array surfance mount package thermal measurements," JEDEC JESD51-9, EIA & JEDEC Solid State Technology Association, 2000.
[83] B. Xiong, M. J. Lee, and T. Kao, "Warpage improvement for large die flip chip package," 11th Electronics Packaging Technology Conference, Singapore, Dec. 9-11, 2009, pp. 40-43
[84] "Temperature cycling," JEDEC JESD22-A104-B, EIA & JEDEC Solid State Technology Association, 2000.
[85] C. M. Liu, C. C. Lee, and K. N. Chiang, "Enhancing the reliability of wafer level packaging by using solder joints layout design," IEEE Transactions on Components and Packaging Technologies, vol. 29, pp. 877-885, 2006.
[86] "NAND flash interface interoperability," JEDEC JESD230, JEDEC Solid State Technology Association, 2012.
[87] M. C. Yew, "Design, structural reliability assessment, and electromigration evaluation for the advanced microelectronic packages," Ph. D Thesis of National Tsing Hua University, 2009.