隨著晶片設計複雜程度提升，為了減輕晶片中邏輯閘的擁擠情況，利用三維空間的概念來創造晶片堆疊的方式已被廣泛討論。為了提升三維晶片的良率，堆疊前測試扮演了極為重要的腳色。堆疊前測試是用來確保每一層晶圓沒有錯誤產生，與傳統二維晶片測試不同的地方在於，三維晶片是採用矽穿通道 (Through-Silicon-Via) 作為層與層之間的溝通，此特性會導致在作堆疊前測試時，由於層與層之間還未堆疊，那些藉由矽穿通道傳遞訊號的連接端口不具備可測試性設計 (Design for Testa-bility) 所須遵循的兩大原則: 可控制與可觀察，使得測試品質降低。而過往在解決此問題的方法為添加測試介面暫存器到每一個矽穿通道的兩端點。然而，此方法會導致電路面積增加使得設計成本上升。在本文中，藉由重複利用已存在電路內的掃描暫存器，並導入圖形理論的概念來有效降低測試介面暫存器的使用數量，而為了避免重複使用掃描暫存器所帶來的時序違規，掃描暫存器的時序資訊以及電路實體位置均被考慮來避免時序違規的發生。實驗結果顯示我們的方法除了能夠有效降低測試介面暫存器的使用，也不會發生時序違規的情況。

Three Dimensional Integrated Circuits (3D-ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas, higher performance and lower power consumption. With the short and dense Through-Silicon-Vias (TSVs), multiple dies can be integrated to overcome the barrier of interconnection. However, before 3D-ICs become a viable technology, the understanding of 3D testing issues is still insufficient and there are still many unresolved testing challenges. To ensure the stack yield of future adopting of 3D-SICs, pre-bond testing is needed to provide the known good die (KGD). Since the TSVs are not fully accessible prior to bonding, testing the combinational logic between the scan flip-flops and TSV becomes a complex issue. In order to overcome the limitation of TSV, additional wrapper cells was proposed to be added at the two ends of TSVs to provide controllability and observability. Even though it is a major breakthrough for pre-bond testing, the wrapper cells used by the TSVs lead to significant area overhead and decrease the system performance. For reducing the number of additional wrapper cells, several approaches have proposed solutions by reusing the existing primary inputs/outputs or scan flip-flops to achieve high testability. However, practical timing considerations were overlooked and the number of inserted wrapper cells was still high. In this work, based on the previous work, we modify its algorithm to produce more number of re-used scan flip-flops. Moreover, by considering practical timing and layout information, our approach does not incur any timing violation. Furthermore, with the help of commercial ATPG tool, the re-usability of scan flip-flops can be maximized. Results are presented for 3D-stack implementations of the ITC’99 benchmark circuits.

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