近年來，奈米點(nanocrystals)的應用發展與基礎研究受到相當大的矚目，尤其當奈米點運用於非揮發性記憶體時，可以解決傳統上利用複晶矽浮停閘(floating gate)做為載子儲存單元的非揮發性記憶體(例如，快閃記憶體)之元件微縮問題。例如:在經過多次資料讀取與寫入過程中所造成的穿隧氧化層漏電路徑，將使得儲存單元中的電荷全部流失，造成記憶體元件功能的失效。因此在元件微縮過程中，穿隧氧化層的厚度將成為限制了元件微縮的重要關鍵之一。再者由於穿隧氧化層無法薄化，於是操作電壓也無法降低，讀取速度也跟著無法增快，這些問題也深深影響著非揮發性記憶體的應用性。但若以奈米點取代浮停閘結構可以解決上述問題，因為電荷僅儲存於分立的(distributed)奈米點中，若穿隧氧化層存在局部的漏電路徑，並不會導致電荷的全部流失，仍能維持記憶元件之功能。在奈米點應用於非揮發性記憶體元件，近年來的研究更著重在金屬奈米點。利用金屬材料來形成奈米點主要原因是因為金屬有以下的優點:金屬擁有較多的功函數可供元件的調變使用;而且在記憶體元件寫入時，金屬奈米點不會造成電壓消耗，使得起始電壓得以降低。在基於省電與低電壓操作的前提下，金屬奈米點具有相當的優越性。
本研究探討金屬鎳、鈷、鎳矽化物及鈷矽化物的奈米點作為非揮發性記憶體儲存電荷中心之效應。金屬鎳與鈷均可利用熱退火500 °C而形成金屬鎳與鈷的奈米點，鎳矽化物及鈷矽化物則是利用熱氧化方式在900 °C下形成鎳矽化物及鈷矽化物之奈米點。在本論文的實驗中，均可在低於6 伏特的操作電壓下得到1伏特的記憶窗口。金屬及金屬矽化物奈米點的操作電壓是低於半導體(Si, Ge)奈米點7-9 伏特的操作電壓。
金屬奈米點藉由改變其介電質材料可以更降低記憶體元件的操作電壓，因為可攜式產品的普及，所以低電壓操作是個很重要的需求。本研究成功的藉由置換不同的介電質材料得到更低的操作電壓。除此之外，也藉由臨場電子顯微鏡直接觀察奈米點的形成，對奈米點的形成有更深入的了解。

The nanocrystals embedded in memory devices as charge storage nodes, instead of typical semiconductor floating gate, can effectively solve the issue of data losing due to the leaky paths present in the tunneling oxide. All stored charges are not easily lost through the few leaky paths, since the charges are stored in discretely distributed nanocrystals. The specific charges stored in the nanocrystals nearby a leaky path will just flow away, but others are maintained in the independent nanocrystals. Thus, memory function can be effectively retained.
In this thesis, the Ni, Co, NiSi2 and CoSi2 nanocrystals have been fabricated as the charge storage nodes for nonvolatile memory. The fabrication temperature of the Ni and Co nanocrystals is 500 °C. On the other hand, the NiSi2 and CoSi2 nanocrystals are formed during thermal oxidation of a-Si/Ni and a-Si/Co structures at 900 °C. The most important advantage using the metal nanocrystals over their semiconductor counterparts is that the metal nanocrystals do not bear a voltage drop from gate voltage. The characteristic means that all the voltages provided from control gate are dropped to tunnel oxide and control oxide. The operating voltages of the memory devices with conventional floating gate and semiconductor nanocrystals embedded in SiO2 are about 7 V and 5 V, respectively.
The metal nanocrystals embedded in the different dielectrics were also studied. By changing the dielectric, the lower operating voltage can be obtained.

References
Chapter 1
[1.1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech, J., 46, 1288-1288 (1967).
[1.2] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introdution to flash memory,” Proc.IEEE, 91, 489-502 (2003).
[1.3] S. Lai, “Flash memories: where we were and where we are going,” IEEE IEDM, Tech. Dig., 971-974 (1998).
[1.4] Y. Yang, A. Purwar, and M. H. White, “Reliability considerations in scaled SONOS nonvolatile memory device,” Solid-State Electronics, 43, 2025-2032 (1999).
[1.5] F. A. Sewell, H.A.R. Wegener, and E. T. Lawis, “Charge storage model for variable FET memory element,” Appl. Phys. Lett., 14, 45-47 (1969).
[1.6] P. Chen, “Threshold-alterable Si-gate MOS devices,” IEEE Trans. Electron Device, 24, 584-586 (1977).
[1.7] M. H. White, Y. Yang, A. Purwar, and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Trans. Comp., Packag., Manufact. Technol. A, 20, 190-195 (1997).
[1.8] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and nonvolatile memories in silicon with nano-crystal storage,” IEEE IEDM Tech. Dig., 521-524 (1995).
[1.9] S. Lai, “Tunnel oxide and ETOX flash scaling limitation,” Proc. Int. Nonvolatile Memory Technology Conf., 6-7 (1998).
[1.10] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett. 68, 1377-1379 (1996).
[1.11] H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nano-crystal memory,” IEEE Trans. Electron Devices 43, 1553-1558 (1996).
[1.12] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories,” Appl. Phys. Lett. 69, 1232-1234 (1996).
[1.13] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory,” IEEE Trans. Electron Device Lett. 18, 278-280 (1997).
[1.14] J. D. Blauwe, “Nanocrystal nonvolatile memory devices,” IEEE Transaction on Nanotechnology 1, 72-77 (2002).
[1.15] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212-1214 (2003).
[1.16] L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M. Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure,” Appl. Phys. Lett. 81, 3639-3641 (2002).
[1.17] V. Craciun, I. W. Boyd, A. H. Reader, and E. W. Vandenhoudt, “Low temperature synthesis of Ge nanocrystals in SiO2,” Appl. Phys. Lett. 65, 3233-3235 (1994).
[1.18] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge,” IEEE IEDM Tech. Dig., 115-118 (1998).
[1.19] K. Das, M. NandaGoswami, R. Mahapatra, G.. S. Kar, H. N. Acharya, S. Maikap, J. H. Lee, and S. K. Ray, “Charge storage and photoluminescence characteristics of silicon oxide embedded Ge nanocrystal trilayer structures,” Appl. Phys. Lett. 84, 1386-1388 (2004).
[1.20] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu and S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Appl. Phys. Lett., 84, 2581-2583 (2004).
[1.21] E. A. Boer, L. D. Bell, M. L. Brongersma, H. A. Atwater, M. L. Ostraat, and R. C. Flagan, “Charging of single Si nanocrystals by atomic force microscopy,” Appl. Phys. Lett. 78, 3133-3135 (2001).
[1.22] S. Banerjee, M.A. Salem, S. Oda, “Conducting-tip atomic force microscopy for injection and probing of localized charges in silicon nanocrystals,” Appl. Phys. Lett. 83, 3788-3790 (2003).
[1.23] S. Decossas, F. Mazen, T. Baron, G. Bremond, A. Soui., “Atomic force microscopy nanomanipulation of silicon nanocrystals for nanodevice fabrication,” Nanotechnology 14, 1272-1278 (2003).
[1.24] K. K. Likharev,” Single-electron devices and their applications,” Proc. IEEE, 87, 606-632 (1999).
[1.25] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, “Non- volatile Si quantum memory with self-aligned doubly-stacked dots,” IEEE Trans. Electron Devices, 49, 1392–1398 (2002).
[1.26] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories. I. Device design and fabrication,” IEEE Trans. Electron Devices 49, 1606-1613 (2002).
Chapter 2
[2.1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells: an overview,” Proceedings of The IEEE, 85, 1248-1271 (1997)
[2.2] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE J. Solid-State Circuits, 14, 442-455 (1979)
[2.3] M.Lenzlinger, “Fowler-Nordheim Tunneling in thermal grown SiO2,” J. App. Phys., 40, 278-283 (1969)
[2.4] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash Memory Cells- An Overview,” Proceedings of The IEEE, 85, 1248-1271 (1997)
[2.5] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory,” Proceedings of the IEEE., 91, 489-502 (2003)
[2.6] K. Kim, J. Choi, “Future Outlook of NAND Flash Technology for 40nm Node and Beyond,” NVSMW, 9-11 (2006)

Chapter 3
[3.1.] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and nonvolatile memories in silicon with nano-crystal storage,” IEEE Int. Electron Devices Meeting Tech. Dig., 521-524 (1995).
[3.2.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part I: DeviceDesign and Fabrication,” IEEE Tran. Electron Devices 49, 1606-1613 (2002).
[3.3.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part II: Electrical Characteristics,” IEEE Trans. Electron Devices 49, 1614-1622 (2002).
[3.4.] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett. 68, 1377-1379 (1996).
[3.5.] H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and Long Retention-Time Nano-Crystal Memory,” IEEE Trans. Electron Devices 43, 1553-1558 (1996).
[3.6.] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories,” Appl. Phys. Lett. 69, 1232-1234 (1996).
[3.7.] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Romm temperature operation of a quantum-dot flash memory,” IEEE Electron Device Lett. 18, 278-280 (1997).
[3.8.] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transaction on Nanotechnology 1, 72-77 (2002).
[3.9.] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212-1214 (2003).
[3.10.] L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M. Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure,” Appl. Phys. Lett. 81, 3639-3641 (2002).
[3.11.] V. Craciun, I. W. Boyd, A. H. Reader, and E. W. Vandenhoudt, “Low temperature synthesis of Ge nanocrystals in SiO2,” Appl. Phys. Lett. 65, 3233-3235 (1994).
[3.12.] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge,” Inter. Electron Devices Meeting Tech. Dig., 115-118 (1998).
[3.13.] K. Das, M. NandaGoswami, R. Mahapatra, G.. S. Kar, H. N. Acharya, S. Maikap, J. H. Lee, and S. K. Ray, “Charge storage and photoluminescence characteristics of silicon oxide embedded Ge nanocrystal trilayer structures,” Appl. Phys. Lett. 84, 1386-1388 (2004).
[3.14.] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu and S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Appl. Phys. Lett., 84, 2581-2583 (2004).
[3.15.] F. W. Lytle, R. B. Greegor, D. R. Sandstrom, E. C. Marques, J. Wong, C. L. Spiro, G. P. Huffman, and F. E. Huggins, “Measurement of soft X-ray absorption spectra with a fluorescent ion chamber detector,” Nucl. Instrum. Methods 226, 542-548 (1984).
[3.16.] P. Zhang and T. K. Sham, “Tuning the electronic behavior of Au nanoparticles with capping molecules,” Appl. Phys. Lett. 81, 736-738 (2002)
[3.17.] S. Y. Ha, J. Park, T. Ohta, G. Kwag, and S. Kim, “In Situ Iron K-Edge XANES Study of Iron Phthalocyanine Irreversibly Adsorbed on an Electrode Surface,” Electrochem. Solid-State Lett. 2, 461-464 (1999).
[3.18.] G. Dalba, P. Fornasini, R. Grisenti, F. Rocca, and I. Chambouleyron, “Local order of Sb and Bi dopants in hydrogenated amorphous germanium thin films studied by extended x-ray absorption fine structure,” Appl. Phys. Lett. 81, 625-627 (2002).
[3.19.] D. N. Kouvatsos, V. L. Sougleridis, and A. G. Nassiopoulou, “Charging effects in silicon nanocrystals within SiO2 layers, fabricated by chemical vapor deposition, oxidation, and annealing,” Appl. Phys. Lett. 82, 397-399 (2003).

Chapter 4
[4.1.] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and nonvolatile memories in silicon with nano-crystal storage,” IEEE Int. Electron Devices Meeting Tech. Dig., 521-524 (1995).
[4.2.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part I: DeviceDesign and Fabrication,” IEEE Tran. Electron Devices 49, 1606-1613 (2002).
[4.3.] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Romm temperature operation of a quantum-dot flash memory,” IEEE Electron Device Lett. 18, 278-280 (1997).
[4.4.] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transaction on Nanotechnology 1, 72-77 (2002).
[4.5.] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212-1214 (2003).
[4.6.] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge,” Inter. Electron Devices Meeting Tech. Dig., 115-118 (1998).
[4.7.] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories,” Appl. Phys. Lett. 69, 1232-1234 (1996).
[4.8.] M. Ostraat, J. De Blauwe, M. Green, D. Bell, H. Atwater, and R. Flagan, “Ultraclean Two-Stage Aerosol Reactor for Production of Oxide-Passivated Silicon Nanoparticles for Novel Memory Devices,” J. Electrochem. Soc., 148, 265-270 (2001).
[4.9.] K. Das, M. NandaGoswami, R. Mahapatra, G.. S. Kar, H. N. Acharya, S. Maikap, J. H. Lee, and S. K. Ray, “Charge storage and photoluminescence characteristics of silicon oxide embedded Ge nanocrystal trilayer structures,” Appl. Phys. Lett. 84, 1386-1388 (2004).
[4.10.] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu and S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Appl. Phys. Lett., 84, 2581-2583 (2004).
[4.11.] D. N. Kouvatsos, V. L. Sougleridis, and A. G. Nassiopoulou, “Charging effects in silicon nanocrystals within SiO2 layers, fabricated by chemical vapor deposition, oxidation, and annealing,” Appl. Phys. Lett. 82, 397-399 (2003).

Chapter 5
[5.1.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part I: DeviceDesign and Fabrication,” IEEE Tran. Electron Devices 49, 1606-1613 (2002).
[5.2.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part II: Electrical Characteristics,” IEEE Trans. Electron Devices 49, 1614-1622 (2002).
[5.3.] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze, “Electron Charging and Discharging Effects of Tungsten Nanocrystals Embedded in Silicon Dioxide for Low-Voltage Nonvolatile Memory Technology,” Electrochem. Solid-State Lett. 8, G71-73 (2005).
[5.4.] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories,” Appl. Phys. Lett. 69, 1232-1234 (1996).
[5.5.] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Romm temperature operation of a quantum-dot flash memory,” IEEE Electron Device Lett. 18, 278-280 (1997).
[5.6.] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transaction on Nanotechnology 1, 72-77 (2002).

Chapter 6
[6.1.] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and nonvolatile memories in silicon with nano-crystal storage,” IEEE Int. Electron Devices Meeting Tech. Dig., 521-524 (1995).
[6.2.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part I: DeviceDesign and Fabrication,” IEEE Tran. Electron Devices 49, 1606-1613 (2002).
[6.3.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part II: Electrical Characteristics,” IEEE Trans. Electron Devices 49, 1614-1622 (2002).
[6.4.] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory,” Appl. Phys. Lett. 68, 1377-1379 (1996).
[6.5.] H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and Long Retention-Time Nano-Crystal Memory,” IEEE Trans. Electron Devices 43, 1553-1558 (1996).
[6.6.] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze, “Electron Charging and Discharging Effects of Tungsten Nanocrystals Embedded in Silicon Dioxide for Low-Voltage Nonvolatile Memory Technology,” Electrochem. Solid-State Lett. 8, G71-73 (2005).
[6.7.] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories,” Appl. Phys. Lett. 69, 1232-1234 (1996).
[6.8.] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Romm temperature operation of a quantum-dot flash memory,” IEEE Electron Device Lett. 18, 278-280 (1997).
[6.9.] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transaction on Nanotechnology 1, 72-77 (2002).
[6.10.] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212-1214 (2003).
[6.11.] L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M. Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure,” Appl. Phys. Lett. 81, 3639-3641 (2002).
[6.12.] V. Craciun, I. W. Boyd, A. H. Reader, and E. W. Vandenhoudt, “Low temperature synthesis of Ge nanocrystals in SiO2,” Appl. Phys. Lett. 65, 3233-3235 (1994).
[6.13.] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge,” Inter. Electron Devices Meeting Tech. Dig., 115-118 (1998).
[6.14.] K. Das, M. NandaGoswami, R. Mahapatra, G.. S. Kar, H. N. Acharya, S. Maikap, J. H. Lee, and S. K. Ray, “Charge storage and photoluminescence characteristics of silicon oxide embedded Ge nanocrystal trilayer structures,” Appl. Phys. Lett. 84, 1386-1388 (2004).
[6.15.] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu and S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Appl. Phys. Lett., 84, 2581-2583 (2004).

Chapter 7
[7.1.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part I: DeviceDesign and Fabrication,” IEEE Tran. Electron Devices 49, 1606-1613 (2002).
[7.2.] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories—Part II: Electrical Characteristics,” IEEE Trans. Electron Devices 49, 1614-1622 (2002).
[7.3.] P. H. Yeh, C. H. Yu, L. J. Chen, H. H. Wu, P. T. Liu and T. C. Chang, “Low power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer,” Appl. Phys. Lett. 87, 193504-193506 (2005).
[7.4.] P. H. Yeh, H. H. Wu, C. H. Yu, L. J. Chen, P. T. Liu, C. H. Hsu and T. C. Chang, “Fabrication of NiSi2 Nanocrystals Embedded in SiO2 with Memory Effect by Oxidation of the Amorphous Si/Ni/SiO2 Structure,” J. Vac. Sci. Technol. A 23, 851-855 (2005).
[7.5.] P. H. Yeh, L. J. Chen, P. T. Liu, D. Y. Wang and T. C. Chang, “Nonvolatile Memory Devices with NiSi2/CoSi2 Nanocrystals,” Journal of Nanoscience and Nanotechnology (2006) accept.