台灣半導體產業卓越的表現與亮眼的成績，使得台灣在全球半導體市場一直居於舉足輕重的關鍵地位，但如何保持既有優勢、創造新的市場格局，便是台灣半導體產業必須面對的課題。在半導體研發設計過程中，研發設計單位會利用WAT測試資料尋找符合最初電路模擬元件設計目標與功能的晶方─黃金晶方，透過這些具代表性的黃金晶方之WAT資料回饋，可加速製程空間的分析，然而由於WAT測試資料分析時間與成本的限制，不易進行黃金晶方的定義與挑選，有鑑於此，本研究建構半導體研發設計階段WAT參數分析模型以協助研發設計單位解決此問題，利用WAT測試資料在晶圓上定義群聚，並以研發設計單位最初定義的黃金晶方為分析基礎，利用類神經網路中自我組織映射網路（SOM）之分群演算法，找到與黃金晶方相似的晶方群，而相似黃金晶方群的搜尋增加WAT資料的回饋，提升分析製程空間的效率。本研究以某知名半導體廠研發階段WAT測試資料，並建立系統以驗證分析模型之效用，經由實證結果顯示，本研究方法可有效找到黃金晶方座落的群聚，並進一步找到相似黃金晶方群，因此本研究所提出之分析方法能輔助研發單位以快速有效率方式分析製程空間，減少研發階段所耗用的時間與人力。

Taiwan's semiconductor industry has played a prominent role in global semiconductor market because of its excellent and outstanding achievements. The new challenge to Taiwan's semiconductor industry is how to maintain the competitive advantages and create a whole new business market. In the semiconductor research and design (R&D) stage, the R&D department would find the golden die that meets simulation performance of circuit design. The analysis of process window can be accelerated by the feedback of wafer acceptance test (WAT) data of the golden die. However, it is difficult to define and select the golden die due to cost restrictions and limited time. Accordingly, this research aims to build a model to analyze WAT data at R&D stage during semiconductor fabrification to help R&D department resolve these problems. In this research, WAT data are collected and utilized to classify dices on a wafer and find similar golden dice based on the pre-defined golden die. Similar golden dices provide much more feedback of WAT data, and then the efficiency of process window analysis can then be improved. Real WAT data at R&D stage during semiconductor fabrification are collected from a famous semiconductor manufacturing company and were experimented through the presented analysis model. The experimental results show that the presented model can successfully find similar golden dice in the cluster that a golden die falls. Therefore, the proposed methodology can help the R&D department analyze process window more quickly and efficiently, and the analysis time and cost are greatly reduced at R&D stage during semiconductor fabrification.

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