在本論文中，提出一個低複雜度高效能聯合收發機的完整設計與實現，包跨從規格研讀、系統模擬，架構設計，再到使用場效可規劃邏輯陣列(FPGA)驗證與實現。

在傳統通訊系統上，使用多輸出多輸入技術可以提高系統效能以及增加資料傳輸率，然而假使通道狀態資訊(channel state information)能夠進一步再發射端獲得，可以達到比傳統上更好的系統效能。本論文提出一個結合發射天線選擇機制(transmitter antenna selection)與幾何平均分解法(GMD)的聯合收發機，採用正交分解偵測器(QR detector)，並且實際應用於有限頻寬回傳的通道上。此架構補償了單用幾何平均分解法在情況不佳的通道下缺陷，進一步改善誤碼率(BER)的效能。從浮點數模擬結果來看，此提出的收發機在使用4x6的發射天線選擇組態，當誤碼率為10-2，i.i.d.通道下，有著比開放迴路的垂直-貝爾實驗室分層空時編碼(V-BLAST)好6dB的訊雜比改善。

從硬體複雜度觀點來看，提出許多修改與簡化架構來節省硬體的使用，包含天線選擇方式的簡化、簡單且健全的正交分解偵測器設計。另外由於回傳頻寬之有限且珍貴的實際限制下，另一挑戰必須在有限頻寬下，達到令人滿意的系統效能，為了克服此問題，我們提出了有效率的預編碼矩陣的量化與重建，經過模擬結果證實，此方法具有低回傳資料率、低硬體複雜度，較短的編碼本(codebook)搜尋時間，與較少的編碼本容量等優點。

最後，將聯合收發機置於場效可規劃邏輯陣列(FPGA)板上做實現以進一步驗證提出的演算法與架構，收發機的最大操作時脈頻率可達到50MHz，而對應的最大資料吞吐量可到達120Mbps，此聯合收發機透過模擬和仿真的結果比對證明了功能的正確性，同時亦呈現了令人滿意的效能。

In this thesis, specification study, system simulation, architecture
design and logic design along with field-programmable gate array (FPGA) implementation of a low
complexity and high performance joint transceiver for MIMO Communications is presented.

Communication systems using MIMO technique is important because of the potential improvements in transmission rate and/or link performance. Recently, wireless system where the channel state information is available at the transmitter through a feedback link has attracted considerable attention since that can achieves better performance than conventional ones. This thesis presents an efficient and practicable MIMO transceiver in which transmitter antenna selection at receiver is applied to QR detector with GMD precoding through limited feedback channel. The method compensates the deficiency of the GMD algorithm under ill-conditioned channel and improves the BER performance further. From the floating-point simulation results, the proposed transceiver can achieve over 6 dB SNR improvement over the open-loop V-BLAST counterparts at BER=$10^{-2}$ under i.i.d. channel as 4 $\times$ 6 transmitter antenna selection is adopted.

Simulations are based on the MIMO fading channel model with white noise. The elements in the channel matrix are assumed i.i.d. complex Gaussian random variable with zero mean and variance of $0.5$ per dimension. Simulations are under flat fading and quasi-stationary environment.

In view of hardware complexity, several modified schemes and hardware
simplifications are presented to save the VLSI design cost. For over $4 \times 5$ antenna selection, the proposed antenna selection scheme can save more than 50\% computational complexity compared with that of the exhausting method. And simple and robust QR detector designed without combining post-processing matrix with satisfactory performance is proposed to reduce computational complexity as well. Moreover, due to practical restrictions, the feedback bandwidth is limited and treasurable, another obstacle to the practical implementation of this scheme is whether or not it performs well when the channel has limited feedback. Hence efficient precoder quantization and reconstruction are also analyzed and evaluated which results in low-rate feedback, low hardware cost, short searching codeword time and less codebook size at the same time. Take a $4 \times 4$ precoding matrix for example, the overhead of feedback bits are substantially reduced from 80 bits with scalar quantization applied to 7 bits that efficient vector quantization is uesd.

Finally, a MIMO joint transceiver hardware platform on a Xilinx FPGA is realized to verify the proposed algorithm and architecture. The maximum operating clock rate of the transceiver can achieve about 50 MHz and the corresponding maximum throughput is 120 Mbps. Simulation results and emulation results present correct function and satisfactory performance of our design.

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