基於IEEE 1500之自動化SoC內嵌核心電路延遲測試整合平台

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研究生：	梁庭維 Ting-Wei Liang
論文名稱：	基於IEEE 1500之自動化SoC內嵌核心電路延遲測試整合平台 An Automatic Core-based Delay Test SoC Integrator Based on IEEE Std.1500
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	50
中文關鍵詞：	系統晶片、測試、延遲錯誤測試
外文關鍵詞：	SoC, Testing, Delay Fault Testing
相關次數：	點閱：2 下載：0
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隨著製程技術的提升，單一晶片上所能擁有的電晶體個數隨著晶片面積的增加及最小長度的縮短而呈現快速成長的趨勢，製造一個擁有數百萬至千萬的電晶體數目的晶片已不再是困難的事，而我們現在可以將一完整系統置放入一晶片內部中，這就是所謂的系統晶片。以這樣的設計方法一個系統將可以被快速的建立。而在這樣的方法中，產生了兩個相對應的腳色，核心提供者(core provider)以及核心使用者(core user)。核心提供者提供設計好可以重新使用的核心，而核心使用者整合各個核心使其成立一個系統。這樣的設計概念衍生出的問題是如何對一個這樣的系統整合各個核心的測試資訊以及施行生產測試。目前已有數個為了解決核心測試整合時的問題的標準被提出來，希望能夠將低核心測試整合時的問題與所需要的努力。而且系統晶片的應用越來越廣泛，且系統晶片中所包含的功能也越趨複雜，特別是在速度規格不斷的提升下，系統晶片的測試也變的更加重要，在與時間有關的錯誤當中我們針對因延遲所造成的錯誤為主要討論的主題，因為在目前的系統晶片測試標準當中，並未支援延遲錯誤測試，本文提出了一個適用於系統晶片測試標準之下的延遲錯誤測試策略，整個架構仍支援原本的系統晶片測試標準，並可應用於系統晶片上多顆核心電路。除此之外，還撰寫一套自動化程式,使其可藉由讀取核心電路的相關檔案，而產生整個系統晶片的測試架構和應用於延遲錯誤的測試平台等檔案，因此達到整個測試流程自動化因而提高效率。

Due to the rapidly increasing capacity of semi-conductor technology, the design methodology has come to a higher level of abstraction. The IEEE 1500 is provided to test functionality of each core in SoC but dose not verify its timing specification. In this thesis, a delay fault test architecture that consists of modified wrappers within a delay-test-aware clock controller based on IEEE 1500, the modified TAP controller and a daisy-chained TAM bus architecture are presented. Besides, an automatic program for generating whole test architecture and a chip level testbench for delay fault testing of cores both stored in Verilog files is proposed. In this way, delay fault testing of cores in core-based SoC design is controlled easily and efficiently.

誌謝……………………………………………………………………I
Abstract………………………………………………………………II
中文摘要………………………………………………………………III
目錄…………………………………………………………………IV
List of Contents…………………………………………………… XI
List of Figures……………………………………………………XIII
List of Tables………………………………………………………XV
Chapter 1. Introduction…………………………………………1
Chapter 2. Preliminary……………………………………………5
   2.1 Based on IEEE Std.1500 A Delay Fault Test Framework…………………………………………… ……………… 5
     2.1.1 Wrapper Boundary Register Modification………6
     2.1.2 Synchronous Control………………………………7
     2.1.3 TAP-like Controller………………………………8
     2.1.4 Clock Controller……………………………………10
     2.1.5 Overall Test Architecture…………………………11
   2.2 Parallel TAM Structures………………………………    12
Chapter 3.  The Proposed Test Architecture for Delay Fault Testing Based on IEEE 1500……………………………………    16
   3.1 The Proposed Test Architecture…………………………16
   3.2 Explanation of Delay Fault Testing Sequence in Multiple Cores……………………………………………………19
   3.3 The Proposed Automatic Program……………………24
Chapter 4.  Case Study…………………………………………30
   4.1 The Overall Test Architecture………………………30
   4.2 Delay Fault Test Sequence in this Application………32
   4.3 The Application of the Proposed Automatic Program…40
   4.4 Estimated Test Application Time………………………43
Chapter 6.  Conclusions & Future Works………………………47
   6.1 Conclusions………………………………………………    47
   6.2 Future Works……………………………………………48
Bibliography………………………………………………………49

                                

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