由於通訊系統中對高速與高品質的通訊傳輸要求逐年增加，因此，近年來多輸入多輸出-正交分頻多工 (MIMO-OFDM) 技術被開發，以滿足這些需求。而為了避免像ML偵測器在硬體設計上造成那樣大量的硬體成本負擔，晶格簡化 (Lattice Reduction) 技術的發展著實能幫助次佳的偵測器能以較低硬體成本的方式降低偵測時的錯誤率。然而，當我們採用較適合運用在實際通訊系統下的基於QR矩陣之相關偵測器用以作傳送訊號的還原工作時，FFT個載波所需要執行的晶格簡化 (Lattice Reduction) 與QR分解之運算仍然造成了很大的負擔。在這篇論文中，我們提出的組合式晶格簡化內插式QR分解架構綜合了內插式QR分解以及LR預處理技術，讓我們提出的架構能充分利用鄰近間載波相干的特性來降低系統中LR的運算量，解決了在多輸入多輸出-正交分頻多工 (MIMO-OFDM) 系統下高硬體實現成本與能量消耗的問題。此外，我們提出的架構藉由適當載波個數選擇，將系統中的所有載波切割成多個群組，讓群組中的載波只有受到群組內頻段相關的特性所影響。且為了硬體上的實現，我們讓一些運算在幾乎不改變錯誤率的情況下，以較低硬體成本的方式設計與實現。最後，我們將我們設計的架構使用Synopsys Design Compiler 的TSMC 90nm CMOS技術作合成，其設計的處理器通量 (throughput) 的部分在我們模擬環境下，有最好的通道相關特性的EPA channel可以達到6.592M matrix/s的傳輸量。而此架構同時預處理6個載波的運算，用以增進後端偵測器偵測結果，其硬體Gate count部分大約是220.68k.

Due to the growing data rate and link quality requirements in recent years, the MIMOOFDMtechniques
are developed to satisfy these demands. Unlike the high hardware cost
like the optimal ML detector needs, the application of lattice-reduction (LR) technique
can assist the sub-optimal detectors improve the detection performance with significantly
lower hardware cost compare with ML demands. However, the FFT-size LR operations
and QR decomposition still cause a big burden for hardware implementation if the
QR-based MIMO detectors are applied.
In this thesis, the adoption of interpolation-based QR decomposition (IQRD) of the
proposed architecture can release the large hardware cost problem caused by QR decomposition
and the cooperation of IQRD with preprocessing LR scheme make the coherent
property between sub-carriers is efficiently utilized. In order to make the proposed design
is applicable to various of channel environments, the processing stage number of the
E-CTLLL operations are set adjustable. In addition, when the appropriate separated
choices are applied, the group scheme makes this design only affected by the channel
correlation characteristic in each group. For efficient hardware implementation, some
processors and calculations with lower hardware cost are substituted for original ones.
Furthermore, the proposed design devoted to promoting the hardware utilization rate of
processors to reduce the hardware cost with sufficient throughput. Actually, according
to the synthesis results by utilizing Synopsys Design Compiler with the Arm cell library
and TSMC 90nm CMOS technology, the throughput of the proposed design can achieve 6.592 M matrix/s in the best case (MS = 6; S = 2 in EPA channel) with gate count
220.68k.

[1] H. Vetter, V. Ponnampalam, M. Sandell, and P. Hoeher, “Fixed complexity LLL
algorithm,” IEEE Transactions on Signal Processing, vol. 57, no. 4, pp. 1634–1637,
2009.
[2] A. Youssef, M. Shabany, and P. Gulak, “VLSI implementation of a hardwareoptimized
lattice reduction algorithm forWiMAX/LTE MIMO detection,” in IEEE
Int. Symp. on Circuits Syst. (ISCAS), 2010, pp. 3541–3544.
[3] X. Cao, “Local maximum likelihood detection method for MIMO systems,” in Int.
Conference on Commun., Circuits Syst., vol. 1, May 2005, pp. 203–206.
[4] D. Wubben, R. Bohnke, V. Kuhn, and K.-D. Kammeyer, “MMSE extension of
V-BLAST based on sorted QR decomposition,” in IEEE 58th Veh. Technol. Con-
ference, vol. 1, Oct. 2003, pp. 508–512.
[5] A. K. Lenstra, H. W. Lenstra, and L. Lovasz, “Factoring polynomials with rational
coefficients,” Math. Annalen, vol. 261, pp. 515–534, 1982.
[6] C.-F. Liao and Y.-H. Huang, “Reduced-complexity LLL algorithm for latticereduction-
aided MIMO detection,” in Conference Rec. of the Forty-Third Asilomar
Conference on Signals, Syst. and Comput., Nov. 2009, pp. 1451–1455.
[7] B. J. Choi, C. ho An, J. Yang, S. hoon Jang, and D. K. Kim, “Complexity reduction
for lattice reduction aided detection in MIMO-OFDM systems,” in The 2nd Int.
Conference on Comput. and Autom. Eng. (ICCAE), vol. 2, Feb. 2010, pp. 801–806.
[8] C.-F. Liao, F.-C. Lan, Y.-H. Huang, and P.-L. Chiu, “Latency-constrained lowcomplexity
lattice reduction for MIMO-OFDM systems,” in IEEE Int. Conference
on Acoust., Speech and Signal Process. (ICASSP), May 2011, pp. 1677–1680.
[9] K.-K. Wong and A. Paulraj, “On the decoding order of MIMO maximum-likelihood
sphere decoder: linear and non-linear receivers,” in IEEE 59th Veh. Technol. Con-
ference, vol. 2, May 2004, pp. 698–702.
[10] M. Shabany and P. Gulak, “Scalable VLSI architecture for K-best lattice decoders,”
in IEEE Int. Symp. on Circuits Syst., May 2008, pp. 940–943.
[11] A. Bjorck and C. C. Paige, “Loss and recapture of orthogonality in the modified
gram-schmidt algorithm,” SIAM J. Matrix Anal. Appl., vol. 13, no. 1, pp. 176–190,
1992.
[12] C. K. Singh, S. H. Prasad, and P. T. Balsara, “VLSI architecture for matrix inversion
using Modified Gram-Schmidt based QR decomposition,” in 20th Int. Confer-
ence on VLSI Des. Held jointly with 6th Int. Conference on Embedded Syst, Jan.
2007, pp. 836–841.
[13] K.-L. Chung and W.-M. Yan, “The complex householder transform,” IEEE Trans-
actions on Signal Processing, vol. 45, no. 9, pp. 2374–2376, Sep. 1997.
[14] Z.-Y. Huang and P.-Y. Tsai, “Efficient implementation of QR decomposition for
gigabit MIMO-OFDM systems,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58,
no. 10, pp. 2531–2542, Oct. 2011.
[15] Y. H. Gan, C. Ling, and W. H. Mow, “Complex lattice reduction algorithm for lowcomplexity
full-diversity mimo detection,” IEEE Transactions on Signal Processing,
vol. 57, no. 7, pp. 2701 –2710, 2009.
[16] 3GPP TS 36.101–User Equipment (UE) radio transmission and reception, 3GPP
Technical Specification, Rev. 8.9.0, 2010.
[17] D. Cescato, M. Borgmann, H. Bolcskei, J. Hansen, and A. Burg, “Interpolationbased
QR decomposition in MIMO-OFDM systems,” in IEEE 6th Workshop on
Signal Process. Advances in Wireless Commun., 2005, pp. 945–949.
[18] L.-W. Chai, P.-L. Chiu, and Y.-H. Huang, “Reduced-complexity interpolationbased
QR decomposition using partial layer mapping,” in IEEE Int. Symp. on
Circuits Syst. (ISCAS), May 2011, pp. 2381–2384.
[19] P.-L. Chiu, L.-Z. Huang, L.-W. Chai, and Y.-H. Huang, “Interpolation-based QR
decomposition and channel estimation processor for MIMO-OFDM system,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 5, pp. 1129–1141, May 2011.
[20] A. Burg, “VLSI Circuits for MIMO Communication Systems,” 2006.