近年來，快閃記憶體被廣泛的使用於許多不同的應用之中。隨著3C產品需求量日已漸增，商業用與嵌入式快閃記憶體的使用量有快速且顯著的成長。尤其是在以利用電池為動力的商品以及其他低功率的產品裡面，常常都可以看到他們的存在。快閃記憶體是一種非揮發性的記憶體，它利用特殊的電荷注入機制，可以用簡單的方法達到寫入或與清除資料的效果，並能夠保證其中所儲存的資料，維持很久的一段時間而不會變動或消失。因為這樣子的特性，快閃記憶體非常適合於大量儲存的設備之中。因此，越來越多的快閃記憶體被大量的製造出來。然而為了要保證足夠的良率，在測試與診斷快閃記憶體上面的成本也會相對的增加。所以說如何降低量產時測試的成本以及提高良率等有關於測試快閃記憶體的問題，是非常重要且需要我們仔細探討的問題我們。
在這篇論文裡面，我們提出了一個有彈性的內建式自我測試電路設計。利用了平行處理的概念以及平行輸出診斷資料的方法，我們的內建式自我測試電路可以達到降低測試時間與診斷資料輸出的次數，以降低測試的成本。除了模擬之外，利用了現場可程式邏輯陣列(FPGA)、邏輯分析儀以及實際商業用264Mbits的AND類型的快閃記憶體，我們也做了一個低成本的診斷系統來驗證我們的電路。利用了這個低成本的診斷系統，我們也可以減少診斷記憶體時花在測試機台上面的時間，進而減少測試與診斷記憶體的成本。我們的電路只有佔據了原本快閃記憶體佈局面積的百分之五，並且使測試時間減少到原來的百分之六十，診斷資料輸出的時間也降低至原本的百分之二十。另外，我們也對記憶體裡面的元件做了一些保護的措施，可以避免訊號雜訊的干擾下，我們的電路對記憶體有錯誤且不必要的動作。從我們的實驗結果中我們發現，像這樣子小面積的自我測試電路是非常適合於快閃記憶體的測試。

Flash memory is widely used in many applications nowadays. Theuse of commodity and embedded Flash memories are growing rapidly as the demand of 3C products increases, especially for the battery-powered devices and other low power devices. Flash memory can be programmed or erased electrically on-line, and retains its stored data for a long time, so it is very suitable for mass storage. The larger the Flash memories we produced, the higher the cost in test and diagnosis in order to guarantee their yield.
Therefore, the testing of Flash memory is an important issue, especially for reducing the test cost and improving the yield for mass production.
In this thesis, we propose a flexible BIST circuit design for Flash memory which can reduce the test time and the diagnostic data shift-out cycles. This is done by performing parallel programming/erasing and parallel shift-out mechanism with error index encoding. We also develop a low-cost prototyping diagnosis system by FPGA, and verify our BIST design with real commercial products. This FPGA-based system can be used to diagnose the Flash memory, eliminating the need for expensive ATE, thus reducing the test cost. Our experimental results show that the BIST scheme with small area overhead is suitable for Flash memory
testing. The area overhead of our BIST circuit is about 0.5%
for a commodity 264Mb AND type stand-alone Flash memory. The
total test time is reduced to 64.4\% compared with the original test time. The parallel shift-out mechanism reduces the shift-out cycles (in diagnosis mode) to 20% compared with the original shift-out cycles. We also propose a device protection mechanism which prevents the internal high voltage generator from being damaged by the noise on reset pin that forces the BIST to reset.

Bibliography
[1] IEEE, IEEE 1005 Standard Definitions and Characterization of FloatingGate Semiconductor
Arrays. Piscataway: IEEE Standards Department, 1999.
[2] S. Mukherjee, T. Chang, R. Pang, M. Knecht, and D. Hu, “A single transistor EEPROM cell
and its implementation in a 512K CMOS EEPROM,” in Proc. IEEE Int. Solid-State Cir. Conf.
(ISSCC), p. 616, 1985.
[3] G. Samachisa, C.-S. Su, Y.-S. Kao, G. Smarandoiu, C. Wang, T. Wong, and C. Hu, “A 128K
flash EEPROM using double-polysilicon technology,” IEEE Journal of Solid-State Circuits,
vol. SC-22, pp. 676 – 683, Oct. 1987.
[4] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tanaka, “A 256K flash EEPROM
using triple polysilicon technology,” in Proc. IEEE Int. Solid-State Cir. Conf. (ISSCC),
vol. XXVIII, pp. 168–169, 335, Feb. 1985.
[5] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra high density EPROM and
flash EEPROM with NAND structure cell,” in Proc. IEEE Int. Solid-State Cir. Conf. (ISSCC),
p. 552, 1987.
[6] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Boston: Kluwer Academic
Publishers, 1999.
[7] M. G. Mohammad, K. K. Saluja, and A. Yap, “Testing flash memories,” in Proc. 13th Int.
Conf. VLSI Design, pp. 406–411, Jan. 2000.
[8] M. G. Mohammad and K. K. Saluja, “Flash memory disturbances: modeling and test,” in
Proc. IEEE VLSI Test Symp. (VTS), (Marina Del Rey, California), pp. 218 –224, Apr. 2001.
[9] J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Processor-based built-in self-test for embedded
DRAM,” IEEE Journal of Solid-State Circuits, pp. 1731–1740, Nov. 1998.
[10] R. Rajsuman, “Testing a system-on-a-chip with embedded microprocessor,” in Proc. Int. Test
Conf. (ITC), pp. 499–508, 1999.
[11] P. Camurati, P. Prinetto, M. S. Reorda, S. Barbagallo, A. Burri, and D. Medina, “Industrial
BIST of embedded RAMs,” IEEE Design & Test of Computers, vol. 12, pp. 86–95, Fall 1995.
[12] J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, “Flash memory
built-in self-test using march-like algorithms,” in Proc. IEEE Int. Workshop on Electronic
Design, Test, and Applications (DELTA), (Christchurch), pp. 137–141, Jan. 2002.
[13] S.-K. Chiu, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Diagonal test and diagnostic schemes
for flash memories,” in Proc. Int. Test Conf. (ITC), (Baltmore), pp. 37–46, Oct. 2002.
[14] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in selftest
and self-diagnosis scheme for embedded SRAM,” in Proc. Ninth IEEE Asian Test Symp.
(ATS), (Taipei), pp. 45–50, Dec. 2000.
[15] V. Mastrocola, G. Palumbo, P. Kumar, F. Pipitone, and G. Introvaia, “Built in self test for low
cost testing of a 60MHz synchronous flash memory,” in Proc. 7th IEEE Int. On-Line Testing
Workshop, (Taormina, Italy), pp. 192–196, July 2001.
[16] P. Bernardi, M. Rebaudengo, M. S. Reorda, and M. Violante, “A P1500-compatible programmable
BIST approach for the test of embedded flash memories,” in Proc. Design, Automation
and Test in Europe (DATE), pp. 720– 725, March 2003.
[17] IEEE, “IEEE P1500 standard for embedded core test (SECT).”
http://grouper.ieee.org/groups/1500/, 2002.
[18] A. K. Sharma, Semiconductor Memories: Technology, Testing, and Reliability. Piscataway:
IEEE Press, 1997.
[19] A. H.-F. Chou, C.-S. Yang, C.-J. Liu, H.-H. Pong, M.-C. Liaw, T.-S. Chao, Y.-C. King, H.-L.
Hwang, and C. C.-H. Hsu, “Comprehensive study on a novel bidirectional tunneling program/
erase nor-type (binor) 3-d flash memory cell,” IEEE Transactions Electron Devices,
vol. 48, pp. 1386– 1393, April 2001.
[20] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—an overview,” Proc. of the
IEEE, vol. 85, pp. 1248–1271, Aug. 1997.
[21] S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Mausouka, “Reliability issues of flash
memory cells,” Proc. of the IEEE, vol. 81, pp. 776–787, May 1993.
[22] K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, “RAMSES-FT: A fault
simulator for flash memory testing and diagnostics,” in Proc. IEEE VLSI Test Symp. (VTS),
(Monterey, California), pp. 281–286, Apr. 2002.
[23] C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin,
“Test scheduling of BISTed memory cores for SOC,” in Proc. 11th IEEE Asian Test Symp.
(ATS), (Guam), pp. 356–361, Nov. 2002.
[24] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Gouda, The
Netherlands: ComTex Publishing, 1998.
[25] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in Proc.
IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Albuquerque), pp. 165–
173, Nov. 1999.
[26] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm generation
for random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), (Montreal),
pp. 291–296, Apr. 2000.
[27] A. J. van de Goor and C. A. Verruijt, “An overview of deterministic functional RAM chip
testing,” ACM Computing Surveys, vol. 22, pp. 5–33, Mar. 1990.
[28] C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, “Error catch and analysis
for semiconductor memories using March tests,” in Proc. IEEE/ACM Int. Conf. Computer-
Aided Design (ICCAD), (San Jose), pp. 468–471, Nov. 2000.
xi